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This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. Thebook concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals.

This book investigates the susceptibility of intrinsic physically unclonable function (PUF) implementations on reconfigurable hardware to optical semi-invasive attacks from the chip backside. It explores different classes of optical attacks, particularly photonic emission analysis, laser fault injection, and optical contactless probing. By applying these techniques, the book demonstrates that the secrets generated by a PUF can be predicted, manipulated or directly probed without affecting the behavior of the PUF. It subsequently discusses the cost and feasibility of launching such attacks against the very latest hardware technologies in a real scenario. The author discusses why PUFs are not tamper-evident in their current configuration, and therefore, PUFs alone cannot raise the security level of key storage. The author then reviews the potential and already implemented countermeasures, which can remedy PUFs'security-related shortcomings and make them resistant to optical side-channeland optical fault attacks. Lastly, by making selected modifications to the functionality of an existing PUF architecture, the book presents a prototype tamper-evident sensor for detecting optical contactless probing attempts.

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where it's most effective, this book: Details the architecture organization of RCS platforms for application-specific workloads Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS Explores the virtualization of RCS architecture from the system and on-chip levels Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints Includes illustrative examples, case studies, homework problems, and references to important literature A solutions manual is available with qualifying course adoption.Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications.Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book: Explores classical FPGA architectures and their supporting tools Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs) Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.

This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G.

This book focuses on the design and testing of large-scale, distributed signal processing systems, with a special emphasis on systems architecture, tooling and best practices. Architecture modeling, model checking, model-based evaluation and model-based design optimization occupy central roles. Target systems with resource constraints on processing, communication or energy supply require non-trivial methodologies to model their non-functional requirements, such as timeliness, robustness, lifetime and “evolution” capacity. Besides the theoretical foundations of the methodology, an engineering process and toolchain are described. Real-world cases illustrate the theory and practice tested by the authors in the course of the European project ARTEMIS DEMANES. The book can be used as a “cookbook” for designers and practitioners working with complex embedded systems like sensor networks for the structural integrity monitoring of steel bridges, and distributed micro-climate control systemsfor greenhouses and smart homes.

As embedded systems become more complex, designers face a number of challenges at different levels: they need to boost performance, while keeping energy consumption as low as possible, they need to reuse existent software code, and at the same time they need to take advantage of the extra logic available in the chip, represented by multiple processors working together. This book describes several strategies to achieve such different and interrelated goals, by the use of adaptability. Coverage includes reconfigurable systems, dynamic optimization techniques such as binary translation and trace reuse, new memory architectures including homogeneous and heterogeneous multiprocessor systems, communication issues and NOCs, fault tolerance against fabrication defects and soft errors, and finally, how one can combine several of these techniques together to achieve higher levels of performance and adaptability. The discussion also includes how to employ specialized software to improve this new adaptive system, and how this new kind of software must be designed and programmed.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

Automated Configuration has long been the subject of intensive research, especially in Artificial Intelligence. It is a pervasive problem to be solved, and it is a good test of various knowledge representation and reasoning techniques. The problem shows up in applications such as various electrical circuit design, utility computing and even concurrent engineering. Automated Configuration Problem Solving defines the ubiquitous problem, illustrates the various solution techniques, and includes a survey using these techniques from the mid-70's until the mid-90's. During this time, various general approaches were developed, and then become more specialized. This book covers the development of the general problem solving techniques for automated configuration, which are based on both published academic work and patents.

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a computation but also about the software flow that supports the design process. The goal of this book is to help designers become comfortable with these issues, and thus be able to exploit the vast opportunities possible with reconfigurable logic.

Evolvability, the ability to respond effectively to change, represents a major challenge to today's high-end embedded systems, such as those developed in the medical domain by Philips Healthcare. These systems are typically developed by multi-disciplinary teams, located around the world, and are in constant need of upgrading to provide new advanced features, to deal with obsolescence, and to exploit emerging enabling technologies. Despite the importance of evolvability for these types of systems, the field has received scant attention from the scientific and engineering communities. Views on Evolvability of Embedded Systems focuses on the topic of evolvability of embedded systems from an applied scientific perspective. In particular, the book describes results from the Darwin project that researched evolvability in the context of Magnetic Resonance Imaging (MRI) systems. This project applied the Industry-as-Laboratory paradigm, in which industry and academia join forces to ensure continuous knowledge and technology transfer during the project's lifetime. The Darwin project was a collaboration between the Embedded Systems Institute, the MRI business unit of Philips Healthcare, Philips Research, and five Dutch universities. Evolvability was addressed from a system engineering perspective by a number of researchers from different disciplines such as software-, electrical- and mechanical engineering, with a clear focus on economic decision making. The research focused on four areas: data mining, reference architectures, mechanisms and patterns for evolvability, in particular visualization & modelling, and economic decision making. Views on Evolvability of Embedded Systems is targeted at both researchers and practitioners; they will not only find a state-of-the-art overview on evolvability research, but also guidelines to make systems more evolvable and new industrially-validated techniques to improve the evolvability of embeddedsystems.

Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable fabric (similar to a field-programmable gate array, FPGA). This book presents novel concepts, strategies, and implementations to increase the run-time adaptivity of reconfigurable embedded processors. Concepts and techniques are presented in an accessible, yet rigorous context. A complex, realistic H.264 video encoder application with a high demand for adaptivity is presented and used as an example for motivation throughout the book. A novel, run-time system is demonstrated to exploit the potential for adaptivity and particular approaches/algorithms are presented to implement it.

This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance Computers (HPC) who may benefit from porting their applications into a reconfigurable environment. As such, this book is intended to guide the HPC user through the many algorithmic considerations, hardware alternatives, usability issues, programming languages, and design tools that need to be understood before embarking on the creation of reconfigurable parallel codes. We hope to show that FPGA acceleration, based on the exploitation of the data parallelism, pipelining and concurrency remains promising in view of the diminishing improvements in traditional processor and system design. Table of Contents: FPGA Technology / Reconfigurable Supercomputing / Algorithmic Considerations / FPGA Programming Languages / Case Study: Sorting / Alternative Technologies and Concluding Remarks

Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.

Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES and DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors.

Introduction in Reconfigurable Computing provides a comprehensive study of the field Reconfigurable Computing. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrin's machine to the very modern architecture like coarse-grained reconfigurable device and the embedded logic devices. Apart from the introduction and the conclusion, the main chapter of the book are the following: Architecture of reconfigurable systems, which presents the technology and the architecture used in fined-grained and those used in coarse-grained reconfigurable devices. Design and implementation: This section deals with the implementation on reconfigurable system. It briefly covers the steps needed to implement application on today's FPGAs. And focus on the logic synthesis for FPGA, in particular LUT technology mapping. High-Level Synthesis for Reconfigurable Devices: The high-level synthesis for reconfigurable systems, also known as temporal partitioning is presented here. Several temporal partitioning techniques are presented and explained. Temporal placement: This section considers stand alone reconfigurable systems. Its assume that a kind of operating systems for reconfigurable systems is in charge of managing the resources of a given system and allocate space on a device for the computation of incoming tasks., and therefore presents several temporal placement approaches for off-line as well as on-line placement. On-line and Dynamic Interconnection: This chapter reviews andexplains the different approaches for allowing communication between modules dynamically placed at run-time on a given device. Designing a reconfigurable application on Xilinx Virtex FPGA: In this section, the different design approaches of partial reconfigurable systems on the Xilinx FPGAs that are one of the few one on the market with this feature, is explained. System on programmable chip: System on programmable chip is a hot topic in reconfigurable computing. This is mainly the integration of a system made upon some peripheral (UART, Ethernet, VGA, etc.), but also computational (Coding, filter, etc.) hardware modules on one programmable chip. The current usable solutions are presented: The book furthermore focusses on the development of adaptive multiprocessors on chip, i.e. systems consisting of a set of Processors and exchangeable hardware accelerators. Applications: This part covers the use of reconfigurable system in computer architecture (rapid prototyping, reconfigurable supercomputer, reconfigurable massively parallel computers) and algorithm better adapted for reconfigurable systems (distributed arithmetic, network packet processing, etc...)

Cryptographic solutions using software methods can be used for those security applications where data traffic is not too large and low encryption rate is tolerable. On the other hand, hardware methods offer high-speed solutions making them highly suitable for applications where data traffic is fast and large data is required to be encrypted in real time. VLSI (also known as ASIC), and FPGAs (Field Programmable Gate Arrays) are two alternatives for implementing cryptographic algorithms in hardware. FPGAs offer several benefits for cryptographic algorithm implementations over VLSI as they offer high flexibility. Due to its reconfigurable property, keys can be changed rapidly. Moreover, basic primitives in most cryptographic algorithms can efficiently be implemented in FPGAs. Since the invention of the Data Encryption Standard (DES), some 40 years ago, a considerable amount of cryptographic algorithm implementation literature has been produced both, for software and hardware platforms. Unfortunately, virtually there exists no book explaining how the main cryptographic algorithms can be implemented on reconfigurable hardware devices. This book will cover the study of computational methods, computer arithmetic algorithms, and design improvement techniques needed to implement efficient cryptographic algorithms in FPGA reconfigurable hardware platforms. The concepts and techniques to be reviewed in this book will make special emphasis on the practical aspects of reconfigurable hardware design, explaining the basic mathematics related and giving a comprehensive description of state-of-the-art implementation techniques. Thus, the main goal of this monograph is to show how high-speed cryptographic algorithms implementations can be achieved on reconfigurable hardware devices without posing prohibited high requirements for hardware resources.

A one-of-a-kind survey of the field of Reconfigurable Computing Gives a comprehensive introduction to a discipline that offers a 10X-100X acceleration of algorithms over microprocessors Discusses the impact of reconfigurable hardware on a wide range of applications: signal and image processing, network security, bioinformatics, and supercomputing Includes the history of the field as well as recent advances Includes an extensive bibliography of primary sources