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Purpose: This paper aims to offer a hybrid genetic algorithm and the ant colony optimization (GA-ACO) algorithm for task mapping and resource management. The paper aims to reduce the makespan and total response time in fog computing- medical cyber-physical system (FC-MCPS). Design/methodology/approach: Swift progress in today's medical technologies has resulted in a new kind of health-care tool and therapy techniques like the MCPS. The MCPS is a smart and reliable mechanism of entrenched clinical equipment applied to check and manage the patients' physiological condition. However, the extensive-delay connections among cloud data centers and medical devices are so problematic. FC has been introduced to handle these problems. It includes a group of near-user edge tools named fog points that are collaborating until executing the processing tasks, such as running applications, reducing the utilization of a momentous bulk of data and distributing the messages. Task mapping is a challenging problem for managing fog-based MCPS. As mapping is an non-deterministic pol ynomial-time-hard optimization issue, this paper has proposed a procedure depending on the hybrid GA-ACO to solve this problem in FC-MCPS. ACO and GA, that is applied in their standard formulation and combined as hybrid meta-heuristics to solve the problem. As such ACO-GA is a hybrid meta-heuristic using ACO as the main approach and GA as the local search. GA-ACO is a memetic algorithm using GA as the main approach and ACO as local search. Findings: MATLAB is used to simulate the proposed method and compare it to the ACO and MACO algorithms. The experimental results have validated the improvement in makespan, which makes the method a suitable one for use in medical and real-time systems. Research limitations/implications: The proposed method can achieve task mapping in FC-MCPS by attaining high efficiency, which is very significant in practice. Practical implications: The proposed approach can achieve the goal of task scheduling in FC-MCPS by attaining the highest total computational efficiency, which is very significant in practice. Originality/value: This research proposes a GA-ACO algorithm to solve the task mapping in FC-MCPS. It is the most significant originality of the paper. [ABSTRACT FROM AUTHOR]

Purpose: Based on the positive features of the shark smell optimization (SSO) algorithm, the purpose of this paper is to propose a method based on this algorithm, dynamic voltage and frequency scaling (DVFS) model and fuzzy logic to minimize the energy consumption of integrated circuits of internet of things (IoT) nodes and maximize the load-balancing among them. Design/methodology/approach: Load balancing is a key problem in any distributed environment such as cloud and IoT. It is useful when a few nodes are overloaded, a few are under-loaded and the remainders are idle without interrupting the functioning. As this problem is known as an NP-hard one and SSO is a powerful meta-hybrid method that inspires shark hunting behavior and their skill to detect and feel the smell of the bait even from far away, in this research, this study have provided a new method to solve this problem using the SSO algorithm. Also, the study have synthesized the fuzzy logic to counterbalance the load distribution. Furthermore, DVFS, as a powerful energy management method, is used to reduce the energy consumption of integrated circuits of IoT nodes such as processor and circuit bus by reducing the frequency. Findings: The outcomes of the simulation have indicated that the proposed method has outperformed the hybrid ant colony optimization – particle swarm optimization and PSO regarding energy consumption. Similarly, it has enhanced the load balance better than the moth flame optimization approach and task execution node assignment algorithm. Research limitations/implications: There are many aspects and features of IoT load-balancing that are beyond the scope of this paper. Also, given that the environment was considered static, future research can be in a dynamic environment. Practical implications: The introduced method is useful for improving the performance of IoT-based applications. We can use these systems to jointly and collaboratively check, handle and control the networks in real-time. Also, the platform can be applied to monitor and control various IoT applications in manufacturing environments such as transportation systems, automated work cells, storage systems and logistics. Originality/value: This study have proposed a novel load balancing technique for decreasing energy consumption using the SSO algorithm and fuzzy logic. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to deal with application of artificial intelligence for solving real time control complication adhered with the controlled operation of a buck power converter. This type of converter finds application for power conversion at various levels for the direct current-direct current power industry to step down the input voltage. Design/methodology/approach: Use of ANN-RL (Artificial Neural Networks- Reinforcement Learning)-based control algorithm to control buck power converter shows robustness against parameter and load variation. Because of non-linearity instigated by element used for switching, control of this converter becomes an arduous control predicament. All the classical control techniques are based on an approximate linear model of the step down converter and these techniques fail to handle actual non-linearity. Findings: In this paper, a reinforcement learning-based algorithm has been used to handle and control buck power converter output voltage, without approximating the model of converter. The non-linearity instigated in converter is subjected to state of switch. Model of buck power converter is defined as a multi-step decision problem so that it can be solved using mathematical model of Markov decision process (MDP) and, in turn, reinforcement learning can be implemented. As MDP model is available for a discrete state system so model of converter has to be discretized and then value iteration is applied and output is analyzed. Load regulation and integral time absolute error analysis is done to show efficacy of this technique. Originality/value: To mitigate the effect of discretization function approximation using neural network is applied. MATrix LABoratory has been used for implementation and result indicates an improvement in the overall response. [ABSTRACT FROM AUTHOR]

Purpose: The privacy of the information is a major challenge in the communication process. In the present modern generation, the cryptography plays a vital role in providing security for data, such as text, images and video while transmitting from source to destination through internet or intranet. The Rivest-Shamir-Adleman (RSA) is an asymmetric key cryptographic system, where the security of the method works on the strength of the key. Design/methodology/approach: In an asymmetric key crypto system, a pair of keys is generated one public key for encryption and one private key for decryption. The major challenge of implementing the RSA is the power function which becomes tedious and time consuming as the exponential value increases. The Chinese remainder theorem proves to be the best for data encryption when it comes to execution time of the algorithm. The proposed novel RSA algorithm with lookup table (LUT) is an extension to the Chinese remainder algorithm, which works better for image and video in terms of time complexity. Findings: This paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods. Originality/value: This paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods. [ABSTRACT FROM AUTHOR]

Purpose: The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach: This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings: This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications: The typical application in this work is PCIe encryption card. Besides server's applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications: It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value: Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this paper is to provide appropriate methods for reducing the abnormalities on the extracted fetal heart signal from the maternal electrocardiogram (ECG). Design/methodology/approach: In this regard, the extracted signal of the fetal heart from the mother, improved using an active noise cancelation (ANC) system. It uses commonly adaptive algorithms of normalized least mean squares (NLMS). In the present paper, fetal extraction and denoising methodology are proposed. This methodology uses a combination of the NLMS algorithm with Savitzky–Golay (S-G) filter. Findings: The obtained results show that a combination of NLMS algorithm with filter coefficient of 15 and µ = 0.02 and S-G filter has a better qSNR (qSNR = 3.6727) and good performance for fetal ECG extraction in comparison with the other works for average fmSNR in the range of −30 to −15 dB. Also, with considering the SNR value of −24.7 dB before filtering and SNR = 3.1861 dB after filtering; the SNR improvement of 27.8861 dB has been obtained. Originality/value: A new method in the extract and noise reduction of fetal ECG from maternal ECG by the combination of NLMS algorithm and S-G filter is proposed. [ABSTRACT FROM AUTHOR]

Purpose: Fall detection is a primary necessity for elderly people with medically tested nervous problems. This paper aims important to detect fall and prevent fatal injuries and untreated attention for long hours. Design/methodology/approach: The project is focused on developing a smart shoe with force-sensitive resistors placed at plantar pressure points to detect fall. This could draw immediate medical attention to the patient. The device is developed using sensors, microcontroller and accelerometer integrated into a compact module. A rule-based detection algorithm helps in transmitting the alert to an Internet of Things device when a fall is detected. Findings: Based on the pressure applied, there is a change in resistive value of force sensitivity resistor. When it reaches the threshold value, fall gets detected and alert gets triggered through telegram bot with latitude and longitude details of the location. Originality/value: The challenge in developing this device is to make it wearable reducing the overall hardware complexity. The entire module placed inside the sole of the shoe avoids inconvenience to the patients. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to examine the design and control of a symmetric multilevel inverter (MLI) using grey wolf optimization and differential evolution algorithms. Design/methodology/approach: The optimal modulation index along with the switching angles are calculated for an 11 level inverter. Harmonics are used to estimate the quality of output voltage and measuring the improvement of the power quality. Findings: The simulation is carried out in MATLAB/Simulink for 11 levels of symmetric MLI and compared with the conventional inverter design. A solar photovoltaic array-based experimental setup is considered to provide the input for symmetric MLI. Field Programmable Gate Array (FPGA) based controller is used to provide the switching pulses for the inverter switches. Originality/value: Attempted to develop a system with different optimization techniques. [ABSTRACT FROM AUTHOR]

Purpose The purpose of this paper is to propose a defect detection method of bare printed circuit boards (PCB) with high accuracy.Design/methodology/approach First, bilateral filtering of the PCB image was performed in the uniform color space, and the copper-clad areas were segmented according to the color difference among different areas. Then, according to the chaotic characteristics of the spatial distribution and the gradient direction of the edge pixels on the boundary of the defective areas, the feature vector, which evaluates quantitatively the significant degree of the defect characteristics by using the gradient direction information entropy and the uniform local binary patterns, was constructed. Finally, support vector machine classifier was used for the identification and localization of the PCB defects.Findings Experimental results show that the proposed algorithm can accurately detect typical defects of the bare PCB, such as short circuit, open circuit, scratches and voids.Originality/value Considering the limitations of describing all kinds of defects on bare PCB by using single kind of feature, the gradient direction information entropy and the local binary patterns were fused to build a feature vector, which evaluates quantitatively the significant degree of the defect features. [ABSTRACT FROM AUTHOR]

Purpose |!|#8211; The purpose of this paper is to propose a new inspecting algorithm for defect detection on PCB circuits. Design/methodology/approach |!|#8211; PCB circuit images were processed by a radon transformation. A Radon histogram was formed and utilized to establish a texture directional characteristic similarity function. Then, a region of the image which contained the same texture directionality feature was segmented. Furthermore, a directionality estimation method is presented. As the circuit was damaged, the directionality was weakened correspondingly. According to principle, the concept of directional intensity was proposed and then used to measure directionality through analysis of the Radon histogram fluctuation. Finally, the defect was detected based on directional intensity. Findings |!|#8211; The method has been applied to an inspecting system used in practice and it achieved a higher accuracy and efficiency in comparison with similar methods. Research limitations/implications |!|#8211; Although work on highly intensive PCB circuitry inspection and flaw detection is presented, defect classification was not involved although this is also a very important requirement of inspection. Originality/value |!|#8211; The paper provides a new way to detect PCB circuitry defects based on texture directionality and proposes evaluating the similarity between image texture directionalities using a radon transformation to search the inspected area. As the inspected region was located, the concept of directional intensity was defined to measure texture directionality to identify defects. The new algorithm performs stably and efficiently and is fit for practical application. [ABSTRACT FROM AUTHOR]

Purpose |!|#8211; The purpose of this paper is to study the application of feature-based image matching algorithm for PCB matching without using special fiducial marks. Design/methodology/approach |!|#8211; Speed-up robust feature (SURF) is applied to extract the interest points in PCB images. An advanced threshold is set to reject the interest points with low responses to speed up feature computation. In order to improve the performance for rotation, the descriptors are based on multi-orientations. The many-to-many tentative correspondences are determined with a maximum distance. Hough transform is used to reject the mismatches and the affine parameters are computed with a square-least solution. Findings |!|#8211; Results show that the method proposed in this paper can match the PCB images without using special fiducial marks effectively. The image matching algorithm shows a better performance for image rotation than the standard SURF and it succeeds in matching the image including repetitive patterns which will deteriorate the distinctiveness of feature descriptors. Research limitations/implications |!|#8211; Additional orientations produce more descriptors so that it takes extra time for feature description and matching. Originality/value |!|#8211; The paper proposes a SURF-based image matching algorithm to match the PCB images without special fiducial marks. This can reduce the complexity of PCB production. The image matching algorithm is robust to image rotation and repetitive patterns and can be used in other applications of image matching. [ABSTRACT FROM AUTHOR]

Purpose |!|#8211; The purpose of this paper is to outline the main features concerning the optimization of printed circuit board (PCB) fabrication by improving the manufacturing process productivity. Design/methodology/approach |!|#8211; The author explored two different approaches to increase the manufacturing process productivity of PCBs. The first approach involved optimization of the PCB manufacturing process as a whole. The second approach was based on increasing the process productivity at the operational level. Findings |!|#8211; To reduce the total manufacturing time, two heuristic algorithms for solving flowshop scheduling problems were designed. These algorithms were used for the computation of an optimal PCB manufacturing schedule. The case study shows both mono- and bi-criteria optimization of the PCBs manufacturing. Research limitations/implications |!|#8211; While the input data used in the case study were based on random numbers, the mathematical considerations drew only the main directions for manufacturing process optimization. Originality/value |!|#8211; The paper shows two original heuristic algorithms for solving the flowshop scheduling problem, with high performance according to the best heuristics in the field. Besides their performances, these algorithms have the advantage of simplicity and ease of implementation on a computer. Using these algorithms, the optimal schedule for the PCB manufacturing process was calculated. For the case of the bi-criteria optimization, the study of points which belong to the Pareto-optimal set are presented. [ABSTRACT FROM AUTHOR]

Purpose – This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach – The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings – The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms. Research limitations/implications – The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications – The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value – Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes. [ABSTRACT FROM AUTHOR]

Purpose To enhance the detection efficiency of printed circuit board (PCB) soldered dot, this study aims to detect PCB soldered dot with image processing method.Design/methodology/approach Through a series of image processing algorithms, threshold segmentation and feature extraction of the solder joint images were completed; then, sphericity was confirmed based on the area and perimeter, as well as the shape parameter and eccentricity ratio of the calculated region, paving the way for defect pattern recognition.Findings It proves that the method with high efficiency and precision can satisfy the requirements of PCB soldered dot detection.Originality/value This paper is original in presenting a method for PCB welding spot detection. [ABSTRACT FROM AUTHOR]