Search

Several 100 Gbps Ethernet standards for backplane, copper cables and fiber optic that include forward error correction based on Reed-Solomon (RS) codes have been recently approved, being an important issue not only to achieve high data rates but also to keep a low latency. This paper presents two low-latency and high-throughput RS decoders suitable for those standards. We propose the use of a modified Enhanced Parallel iBM Algorithm as the key equation solver (KES) stage and a novel architecture for the error evaluation block, which is suited for this KES. Implementation results are given for the RS(528,514) and RS(544,514) codes over GF(210) that reach 100 Gbps when implemented in a 90 nm CMOS process. [ABSTRACT FROM AUTHOR]

Wireless communication standards make use of parallel turbo decoder for higher data rate at the cost of large hardware resources. This paper presents a memory-reduced back-trace technique, which is based on a new method of estimating backward-recursion factors, for the maximum a posteriori probability (MAP) decoding. Mathematical reformulations of branch-metric equations are performed to reduce the memory requirement of branch metrics for each trellis stage. Subsequently, an architecture of MAP decoder and its scheduling based on the proposed back trace as well as branch-metric reformulation are presented in this work. Comparative analysis of bit-error-rate (BER) performances in additive white Gaussian noise channel environment for MAP as well as parallel turbo decoders are carried out. It has shown that a MAP decoder with a code rate of 1/2 and a parallel turbo decoder with a code rate of 1/3 have achieved coding gains of 1.28 dB at a BER of 10 $$^{-5}$$ and of 0.4 dB at a BER of 10 $$^{-4}$$ , respectively. In order to meet high-data-rate benchmarks of recently deployed wireless communication standards, very large scale integration implementations of parallel turbo decoder with 8-64 MAP decoders have been reported. Thereby, savings of hardware resources by such parallel turbo decoders based on the suggested memory-reduced techniques are accounted in terms of complementary metal oxide semiconductor transistor count. It has shown that the parallel turbo decoder with 32 and 64 MAP decoders has shown hardware savings of 34 and 44 % respectively. [ABSTRACT FROM AUTHOR]