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This paper proposes the systolic decoder for Reed-Solomon (RS) codes based on systolic algorithms. Three steps of decoding procedures for RS codes can be reduced to simple repetitive algorithms and thus can be realized by one-dimensional systolic arrays, each operated by simple controls. The decoding system is a cascade connection of these cell arrays in one dimension. In this paper we also design three types of cells building arrays for RS codes on GF(28). Each cell has a size that permits its integration in a one-chip LSI and we can determine the number of cells according to the error correcting ability for codes. [ABSTRACT FROM AUTHOR]

Recently, for the improvement of reliability of digital communication systems, various kinds of error-correcting codes are being used. To improve system reliability through the use of more capable error-correcting codes it is extremely important to simplify the decoder construction and to reduce the decoding delay. This paper studies a decoding algorithm for a class of simple iterated codes (SI codes) constructed by simply repeating I times a codeword (called block) in a given code (called subcode). Moreover, this paper discusses the decoding delay when this decoding algorithm is applied to decoding the Reed-Muller codes constructed by the superimposing method. [ABSTRACT FROM AUTHOR]

This paper proposes a method of constructing nonlinear cyclic codes that form an additive group for which the decoding complexity or error correcting performance is improved relative to RS codes, which are typical linear cyclic codes. First, a code with information digit count k = 1 is constructed by using multiple RS code basis vectors obtained from Galois field Fourier transforms. Then, for k 1, codes are constructed from this code by using idempotent elements. Also, a code with code length n = 7 was constructed as an example, and both its minimal trellis diagram complexity and bit error rate on the AWGN channel due to a computer simulation were shown to be excellent. In addition, an iterative decoder was applied to the codes with k = 4 and 5, which had peak trellis diagram complexity, and it was shown that the decoding complexity could be reduced. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 86(7): 64–73, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.1170 [ABSTRACT FROM AUTHOR]

It is known that by applying a soft decoding algorithm to the error-detecting code in the ARQ system, a hybrid ARQ system can be realized in which error detection and correction are possible. This paper discusses the application of the soft decoding algorithm to the ARQ system, where the multi-valued digital modulation is employed. A scheme for a practical system is proposed, including the detection of channel measurement information in the multivalued digital modulation system and estimation of error patterns. By the proposed method, the hybrid ARQ system can easily be realized by adding some peripheral circuits to the conventional ARQ receiver. Theoretical study is made on the number of error patterns that can be estimated for a long block length as well as the probability of miss and the probability of retransmission request. The proposed scheme was applied experimentally to the ARQ system employing SG VIII V.29 modem based on CCITT recommendation, and the usefulness of the proposed scheme was verified by experiment. [ABSTRACT FROM AUTHOR]