Search

Soft decision decoding is a decoding method which can cut the decoding error probability as compared with hard decision decoding by utilizing the channel measurement information effectively. In this paper, a new soft decision decoding method by which decoding operations can be efficiently carried out by utilizing the hierarchy of linear block codes is proposed. In addition, an improved algorithm which can reduce significantly the maximum computational complexity is also proposed. The proposed decoding algorithm utilizing the hierarchical structure of codes is a decoding method by which decoding is carried out sequentially from codes with high coding rates or codes of higher hierarchy in the inclusion order, and soft decision decoding can be efficiently carried out by utilizing a number of classes of codes having inclusion relationships in a manner which is superior to Chase algorithm 2 in the decoding error probability and the computational complexity for decoding. Computer simulation results confirm that the proposed algorithm realizes decoding error probability characteristics close to those of the maximum likelihood decoding method and that decoding can be carried out efficiently at a lower computational complexity than Chase algorithm 2 when the SNR is large. In addition, the improved algorithm which can reduce significantly the maximum computational complexity can realize decoding error probability characteristics close to those of the maximum likelihood decoding method on practical communication channels with relatively large SNR. © 1999 Scripta Technica, Electron Comm Jpn Pt 3, 83(3): 108–114, 2000 [ABSTRACT FROM AUTHOR]

The real-time processing of the recursive least-square algorithm is difficult to execute by the conventional Neumann-type processor because of its large computational complexity. On the other hand, it is known that the recursive least-square algorithm based on the UD decomposition, which is equivalent to the recursive least-square algorithm, can be realized by the systolic array proposed by Rung. The systolic array to execute this algorithm is difficult to realize since it requires a tremendous number of elements and corrections. In the construction of the dedicated hardware, in general, the word length of the processor affects the processing speed and the hardware area. From such a viewpoint, it is important in the construction of the systolic array to execute the recursive least-square algorithm based on the UD decomposition that the word length of the processor should be minimized. To evaluate the word length, an error analysis is required for the finite word length operation of the recursive least-square algorithm based on the UD decomposition. This paper presents the finite word length floating-point error analysis for the recursive least-square algorithm, based on the UD decomposition, and evaluates the operation error. Then the convergence of the algorithm and the number of updates of the algorithm are evaluated analytically. Finally, by a computer simulation, the validity of the theoretical analysis for the convergence and the number of updates is verified. [ABSTRACT FROM AUTHOR]