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Flip chip packaging faces two primary bondingprocess obstacles: flux use and geometry mismatch between die and substrate pad pitch. These obstacles motivated the development of a fluxless bonding method called solid-liquid inter-diffusion bonding by compressive force (SLICF). SLICF utilizes a mechanical force to form the bond through solid-liquid interdiffusion with a joint-in-via (JIV) architecture for flip chip packaging. SLICF bonding (also known as thermo-mechanical (TM) bonding) forms an instantaneous bond and eliminates the need for reflow infrastructure. Both Au-PbSn and Au-SAC interconnect systems were studied for the SLICF bonding on the JIV architecture at a 130μm pitch. The morphologies of Au-PbSn and Au-SAC in solid-liquid interdiffusion were studied with their kinetics measured by the Au consumption rate. The SLIFC bonds for Au-PbSn and Au-SAC were compared and assessed by mechanical shear tests and thermomechanical stresses. Au with PbSn was found to perform marginally better due to its joint geometry and slower kinetics. [ABSTRACT FROM AUTHOR]

It is believed that the slower-than-expected adoption of flip-chip (FC) packages is due to the lagging advancement in substrate designs and technologies with front-end processes. This lag has also resulted in the need for a costly redistribution layer (RDL), which fans out the die pads to meet the substrate design rule. This paper reviews the photographic metallization limitation of organic substrates and proposes an innovative joint-in-via architecture using existing substrate technologies to improve the pad pitch resolutions. The joint-in-via architecture consolidates the landing pads, the microvias, and the flip-chip joint into one common element, thereby saving valuable substrate real estate for high-density routing. It has been successfully conceptualized on a flex laminate at a pad pitch of 70 μm and a receiving pad size of 50 μm, potentially enabling the removal of the RDL layer for packaging. Robustness in flip-chip assembly is improved by the joint-in-via architecture as it prevents solder bridging and allows the use of existing packaging infrastructure. A new flip-chip chip-scale package (FC-CSP) has evolved with the implementation of the joint-in-via architecture. With material optimization, the FC-CSP passes standard reliability tests, further demonstrating the robustness of the joint-in-via technology. [ABSTRACT FROM AUTHOR]

A correction to the article "A Novel Joint-in-Via Flip-Chip Chip-Scale Package" that was published in the February 2006 issue is presented.