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Chaotic image encryption is widely used in the field of information security. This paper proposes a novel chaotic image encryption method with spiral-transform-based fractal sorting matrix (STFSM). First of all, the theory of STFSM with good scrambling effect is introduced, which has good irregularity and iterative. Then, the iterative algorithm and calculation example of STFSM are introduced. STFSM can be used as the map of spatial location transformations to implement the design of image encryption. Based on the complete STFSM theory and iterative algorithm, a chaotic image cryptosystem based on STFSM is proposed to achieve a good image encryption process. To test the security of the proposed algorithm, security tests and analyses such as entropy analysis, correlation analysis, resistance to differential attacks analysis, and robustness analysis are used for the proposed algorithm. The experimental analysis illustrates that the algorithm has a better encryption effect, whether using conventional tests or the attacks simulations described in this paper and can also effectively resist the attacks. [ABSTRACT FROM AUTHOR]

The 5G edge computing infrastructure should be empowered with quantum attack resistance by implementing post-quantum cryptography (PQC). Among various PQC schemes, lattice-based cryptography (LBC) based on learning with error (LWE) has attracted much attention because of its performance efficiency and security guarantee. In LWE-based LBCs, the Module-LWE-based schemes gain advantage over the others benefiting from the unique polynomial matrix and vector structure. To provide a high-performance implementation of Module-LWE applications for the edge computing paradigm, we propose a domain-specific processor based on a matrix extension of RISC-V architecture. This custom extension encapsulates the matrix-based ring operations with a high-level functional abstraction. A 2-D systolic array with configurable functionality is proposed to perform matrix-based number theoretic transform (NTT) and other arithmetic operations, achieving high data-level parallelism with support for the variable-sized polynomial matrix and vector structure. As this structure of Module-LWE involves no data dependency between different inner elements, an out-of-order mechanism is further developed to exploit the instruction-level parallelism. We implement the proposed architecture under TSMC 28nm technology. The evaluation results show that our implementation can achieve up to $3.5\times $ and $3.3\times $ improvement in cycle count respectively in Kyber and Dilithium, compared to the state-of-the-art crypto-processor counterparts. [ABSTRACT FROM AUTHOR]