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Many energy harvesters (EH) deliver an ac voltage and require a rectifier as a consequence. This paper describes how the rectifier affects the power flow transmitted from the EH to the load and how to tackle the different voltage amplitudes. This study has been performed using analytical calculations, numerical modeling and experiments. To reach the maximum power transfer, conventional methods apply a fraction of the open-circuit voltage delivered by the EH. In contrast, this study points out that the optimum operating point must be shifted by a quantity depending on the rectifier characteristics. This difference is particularly important when the EH provides relatively small ac voltages. Two classic rectifiers are covered: a diode bridge (DB) and a MOSFET bridge (MB). An approximated solution of the analytical model is proposed and allows to optimize the EH without cumbersome numerical computations. Experiments are conducted first with a function generator and then with an electromagnetic EH prototype. The outcomes from the analytical model and the numerical model are in good agreement with the experimental results. A new regulation method is proposed for maximizing the power transferred from the ac EH to the load. [ABSTRACT FROM AUTHOR]

Setting retail electricity prices is one of the significant strategies for energy management of multi-microgrid (MMG) systems integrated with renewable energy. Nevertheless, the need of privacy preservation, the uncertainties of renewable energy and loads, as well as the time-varying scenarios, bring challenges for pricing problems. In this paper, a two-level pricing framework is proposed based on interval predictions and model-free reinforcement learning to address these challenges. In particular, at the higher level, the distribution system operator (DSO) is viewed as an agent, which sets retail electricity prices without detailed user information for privacy protection to maximize the total revenue from selling energy with reinforcement learning. For time-varying scenarios with intermittent photovoltaic power generation and diverse loads, a differentiable trust region layer is considered in reinforcement learning to improve the robustness of the policy updating process. While at the lower level, operators in microgrids solve three-phase unbalanced optimal power flow (OPF) problems to minimize generation cost and network power loss. Additionally, to deal with the challenges from the uncertainties of renewable power generation and user loads, interval predictions are chosen to quantify prediction errors and improve the flexibility of pricing policies. Finally, a set of experiments are conducted to validate the effectiveness of the proposed method for pricing problems in MMG systems. [ABSTRACT FROM AUTHOR]

In this paper, we develop a network-based model with consideration of the physical power flow process to study the cascading failure in cyber-coupled power systems. We take the coupling between power and cyber networks as being resulted from the interdependence of power nodes and cyber nodes. Interaction between two processes, one aiming to attack (cause damage) and the other aiming to defend (protect) the components in the power network, is considered in the model. This interaction offers a novel perspective to interpreting the interdependence of power and cyber networks. To study how an attacker or defender deploys resources to attack or protect a power component, four strategies in distributing the attack and defense strengths are considered, namely, even distribution, degree-based distribution, capacity-based distribution, and random distribution. To probe into the actual propagation process of a blackout, we define four critical time points, namely, start time, attack time, isolation time and end time, and use these time points to analyze and evaluate the effectiveness of different attack and defense strategies. The tit-for-tat defense strategy, in which defender adopts the same strategy as the attacker, is found to be the preferred defense strategy under most conditions. Moreover, allocating defense strength in terms of capacity-based distribution can most effectively suppress cascading failure. This finding was not obtainable without due consideration of the physical power flow process in network-based models. [ABSTRACT FROM AUTHOR]

This paper presents a novel control technique for a wide output voltage range digitally controlled SIDO boost converter. It employs minimum phase conditions reported in refid="ref1"/ , refid="ref2"/ and extends the same to SIDO boost converter to eliminate the effect of RHP zero. Further, the proposed work employs input-output linearization technique refid="ref3"/, refid="ref4"/ to linearize the control-to-output transfer function across different operating points to achieve improved stability under unbalanced loads and a wide output voltage range on each output of the proposed SIDO boost power converter. The SIDO boost regulator was verified experimentally for an input voltage of 3.3 V and a maximum simultaneous load current of 350 mA on each output. Measurement results demonstrate that the proposed design achieves a wide output voltage range of 4.8 V–13.75 V, with ability to dynamically transition across these different output voltages in both small and big voltage steps. [ABSTRACT FROM AUTHOR]

In this paper we give an answer to the following question. Given a multi-port, linear ac network with instantaneous constant-power loads identify a set of active and reactive load powers for which there is no steady-state operating condition of the network—in this case, we say that the power load is inadmissible. The identification is given in terms of feasibility of simple linear matrix inequalities, and hence it can be easily verified with existing software. For one- or two-port networks, the proposed feasibility test is necessary and sufficient for load power admissibility with the test for the former case depending only on the network data. Two benchmark numerical examples illustrate our results. [ABSTRACT FROM PUBLISHER]

The charge pump phase locked loop (CP-PLL) is widely used subsystem in modern mixed-signal electronic systems that are utilized in digital and wireless applications such as clock generation, synchronization and frequency synthesis. In the classical mode, the combination of a current switched charge pump and a digital phase and frequency detector (CP-PFD) circuits produces an ideal pulse width modulated constant current during one sampling period, which permits a suitable transient performance. Nevertheless, many commercially used CP-PLL chips (e.g., 4046 family) have a voltage switched charge pump (VSCP) because the design of the constant voltage source is easier than the constant current generator and it is a low cost solution. However, the VSCP delivers a non-constant pump current, which varies during one sampling period related to the electrical load of the loop filter (LF). This effect results in a varying gain of the control system affecting significantly its tracking ability. Furthermore, due to its hybrid structure, the simulation of the CP-PLL at high frequencies is challenging and the analysis of its transient characteristics during its non-linear acquisition procedure is not easy. In this paper, a first ever exact and nonlinear model based on the phase equations of the second order voltage switched charge pump phase locked loop (VSCP-PLL) is established by using an event driven (ED) technique. This exact model is then simplified by using a step-wise quasi-constant current approximation during one sampling period to obtain the analytical phase equations. The derived ED-model is validated at transistor level simulations using 130 nm CMOS process. Furthermore, some typical nonlinear features of the VSCP-PLL are explored and the developed ED-models are compared with the quasi-time-continuous (QTC) theory. [ABSTRACT FROM PUBLISHER]

A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme that can tolerate supply noise and improve performance when implemented with an integrated voltage regulator (IVR). Measurements from a ‘brain’ SoC, implemented in 40 nm CMOS, demonstrate 2\times performance improvement with adaptive-frequency clocking over conventional fixed-frequency clocking. Combining adaptive-frequency clocking with open-loop IVR extends error-free operation to a wider battery voltage range (2.8 to 3.8 V) with higher average performance. [ABSTRACT FROM AUTHOR]

This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation capacitance (C_C) of 8 pF for a load capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 \muA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA load current. It can settle in less than 1.7 \mus with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/C_C ratio with respect to the counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a systematic classification of auxiliary circuit schemes for feeding fast load transients in switching power converters. The classification is based on the types of the implementation methods, practical constraints and performance. In particular, auxiliary circuits are classified according to the ways in which they are connected with the power supplies and loads, as well as the choice of control methods. Designed as a shunt output, the “intruding” type of auxiliary circuits is effective and less dissipative. Moreover, to reduce complexity, auxiliary circuits may be designed in the form of a bridge output, and employs a “non-intruding” type of control scheme. Furthermore, provision of pre-informed loading condition leads to further simplification of auxiliary circuitry and improvement of efficiency. Experimental measurements are provided to support the analysis of the properties of various types of circuits. [ABSTRACT FROM PUBLISHER]

An ultra-low quiescent current output-capacitorless low-dropout (OCL-LDO) regulator with adaptive power transistors technique is presented in this paper. The proposed technique permits the regulator to transform itself between 2-stage and 3-stage cascaded topologies with respective power transistor, depending on the load current condition. As such, it enables the OCL-LDO regulator to achieve ultra-low power consumption, high stability and good transient response without the need of off-chip capacitor at the output. The proposed LDO regulator has been implemented and fabricated in a UMC 65-nm CMOS process. It occupies an active area of 0.017 mm^2. The measured results have shown that the proposed circuit consumes a quiescent current of 0.9 \muA at no load, regulating the output at 1 V from a voltage supply of 1.2 V. It achieves full range stability from 0 to 100 mA load current at a maximum 100 pF parasitic capacitance load. The measured transient output voltage is 68.8 mV when load current is stepped from 0 to 100 mA in 300 ns with CL = 100 pF. The recovery time is about 6 \mus. Compared to previously reported counterparts, the proposed OCL-LDO regulator shows a significant improvement in term of OCL-LDO transient figure-of-merit (FOM) as well as balanced performance parameters in terms of PSR, line regulation and load regulation. [ABSTRACT FROM PUBLISHER]

Optimal power flow (OPF) problem has already been attempted as a static optimization problem, by adopting conventional gradient-based methods and more recently, nonconventional ones, such as evolutionary algorithms. However, as the loads, generation capacities and network connections in a power system are always in a changing status, these static-oriented methods are of limited use for this issue. This paper presents a new algorithm, dynamic bacterial foraging algorithm (DBFA), for solving an OPF problem in a dynamic environment in which system loads are changing. DBFA is based on the recently proposed BFA which mimics the basic foraging behavior of E. coli bacteria. A selection scheme for bacteria's reproduction is employed in DBFA, which explores the self-adaptability of each bacterium in the group searching activities. DBFA has been evaluated, for optimizing the power system fuel cost with the OPF embedded, on the standard IEEE 30-bus and 118-bus test systems, respectively, with a range of load changes which occurred in different probabilities. The simulation results show that DBFA can more rapidly adapt to load changes, and more closely trace the global optimum of the system fuel cost, in comparison with BFA and particle swarm optimizer. [ABSTRACT FROM AUTHOR]

This paper presents a potential algorithm based on continuation power flow (CPFLOW) to compute all the Type-i load-flow solutions. "type-1 solutions are of a single positive real-part eigenvalue associated with Jacobian of load-flow equations and are used in conjunction with techniques such as energy methods and the voltage instability proximity index (VIPI) for assessing system voltage stability. The benefits of the proposed algorithm are the following. The algorithm has the potential to find all the Type-1 load-flow solutions by tracing a small number of homotopy curves. Traditional methods, which can locate some of the type-1 solutions, suffer from the uncertainty that there might be another Type-1 solution that might be more suitable for voltage stability assessment. This uncertainty is eliminated if all the Type-1 solutions are located. The proposed algorithm has been tested for two example systems, and encouraging results have been obtained. [ABSTRACT FROM AUTHOR]

In this paper, we propose a continuum model for real power systems that tend to be highly irregular in terms of their geographical topology and the power injections, loads, and shunt elements at the bus locations. The continuum model presented here therefore relaxes the isotropy and homogeneity constraints assumed in our prior work. The network, with its transmission lines, generators, and loads, are treated as a continuum in spatial coordinates. We are consequently able to model the system as a pair of nonlinear partial differential equations (PDEs). The first PDE is the continuum equivalent of the load flow equations of the power system and is a boundary value problem. The second equation is the continuum equivalent of the swing equations of the power system. The parameters of these equations are functions of spatial coordinates and the network topology is embedded in them. The computational effort needed to solve the PDEs depends on the uniformity in the parameter distributions. A systematic approach of smoothening the parameter distributions is also proposed. While a continuum system with these smooth parameter distributions looses some of its ability to accurately model the detailed behavior of the power system, the global behavior of the system remains preserved. Furthermore, the electromechanical wave propagation behavior observed in actual power systems is readily recognized from the PDE model. A theoretical analysis of the continuum model as well as test simulations show that disturbances in the system's phase angles propagate through the continuum system with velocities much slower than the speed of light and exhibit dispersion phenomena. [ABSTRACT FROM AUTHOR]

The generalized CMRR analysis of the CMOS current feedback instrumentation amplifier (CFIA), in drain and source feedback configurations (termed DCFIA and SCFIA), is developed by focusing on the input stage. The random CMRR for processes (CMRRP) of the CFIAs are derived as a function of the transistor dimensions, small-signal and operating parameters, as well as the process-dependent mismatch factors, to gain insights into the statistical CMRR characteristics, which enables better design optimization. Simplification of the analysis based on practical constraints yields closed-form CMRRP equations that reveal different design considerations for the two CFIA configurations. For example, while the DCFIA relies on the matching of the input transistors, the matching of the drain load transistors is critical for CMRRP enhancement of the SCFIA (this criterion differs from established design practice). The analysis also reveals that unlike the SCFIA, the DCFIA features a direct tradeoff between noise and CMRRP. The integrity of the analysis is validated by comparison with simulations of various published CFIAs designed in a 0.35-\mum CMOS process. [ABSTRACT FROM AUTHOR]

A high efficiency 3.3 V-to-1 V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (CF1, CF2 =0.1\ \muF) and one output capacitor (COUT =1\ \muF). The peak conversion efficiency is 89% compared to the ideal value of 91% (3* VOUT/VIN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV. [ABSTRACT FROM PUBLISHER]

Wireless power transfer provides a safe and robust way for powering biomedical implants, where high efficiency is of great importance. A new wireless power transfer technique using optimal resonant load transformation is presented with significantly improved efficiency at the cost of only one additional chip inductor component. The optimal resonant load condition for the maximized power transfer efficiency is explained. The proposed technique is implemented using printed spiral coils with discrete surface mount components at 13.56 MHz power carrier frequency. With an implantable coil having an area of 25 mm \times\,10 mm and a thickness of 0.5 mm, the power transfer efficiency of 58% is achieved in the tissue environment at 10-mm distance from the external coil. Compared to previous works, the power efficiency is much higher and the structure is compact with planar integration, easy to tune, and suitable for batch production, as well as biocompatible owing to no incorporation of ferromagnetic core. [ABSTRACT FROM PUBLISHER]

In this article bifurcation analysis of the 9 bus power system model corresponding to the Western Systems Coordinating Council is performed. In order to use standard continuation packages like MATCONT, a full ordinary differential equations model, including the corresponding dynamics of the control loops and the transmission lines, is derived. Different loading conditions are studied by using the load demands as bifurcation parameters. For variations of one of the loads, it is shown that the equilibrium point undergoes Hopf and saddle-node bifurcations. Furthermore, the bifurcation analysis varying two loads simultaneously reveals the existence of a pair of double Hopf and a zero-Hopf bifurcations, acting as organizing centers of the dynamics. Finally, a power system stabilizer has been added in order to modify the location of a Hopf bifurcation curve. [ABSTRACT FROM AUTHOR]

The power efficiency of a RF Class-D amplifier with a bandpass sigma-delta (ΣΔM) modulator is analyzed for a complementary voltage-switched configuration. The modulator broadens the application of the amplifier to include signals with time varying envelopes such as W-CDMA. The addition of a modulator introduces new design variables which affect amplifier power efficiency including coding efficiency and the average transition frequency of the pulse train. Design equations are derived for the optimum load impedance, output power, conduction losses, capacitive switching losses, and drain efficiency. The general design equations are consistent with both periodic and aperiodic drive signals. Analytic and simulated results are compared for an example design with pseudomorphic high-electron mobility transistor and metal-semiconductor field-effect transistor switches with a fourth-order bandpass ΣΔM. The results show a drain efficiency of 52% with a 10-dB peak-to-average power ratio W-CDMA source signal at a frequency of 500 MHz. [ABSTRACT FROM AUTHOR]

Design equations for satisfying the off-nominal operating condition [i.e., only the zero-voltage switching (ZVS) condition] of the Class-E amplifier with a linear shunt capacitance at a duty ratio D = 0.5 are derived. A new parameter s (V/s), called the slope of switch voltage when the switch turns on is introduced to obtain an image of the distance from the nominal conditions. By examining off-nominal Class-E operation degree of the design freedom of the Class-E amplifier increases by one. In addition various amplifier parameters such as operating frequency, output power, and load resistance range can be set as design specifications. For example, the peak switch voltage and switch current can be taken into account in the design procedure. Examples of a design procedure of the Class-E amplifier for off-nominal operation are given. The theoretical results were verified with PSpice simulation and experiments. [ABSTRACT FROM AUTHOR]