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In this paper, we demonstrate how latency insertion method (LIM) can be used for real-time simulation of high switching frequency power electronics systems and how this approach can be implemented for scalable Field Programmable Gate Array (FPGA) execution. We first present a summary of the LIM and how this method can be developed into a solver for high-performance FPGA execution. We then present how common power electronics topologies—buck and boost—can be modeled using the LIM approach, followed by how the LIM model of a three-phase dc/ac converter is created. Afterward, we demonstrate the accuracy of the developed FPGA solver through a set of power electronic system examples, with each example compared with near ideal results of same example provided by a traditional electromagnetic transient type solver. We complete the paper analyzing the scalability of the proposed approach on FPGA devices, both in terms of achievable time step as well as of resource usage. [ABSTRACT FROM AUTHOR]

A recently reported modeling methods for a switched capacitor converter either assume output as “firm” voltage or a resistor to facilitate calculation. When the size of output filter capacitor is moderate, accompanied by noticeable output ripple, previous modeling results may not provide accurate prediction and design guidelines. In this paper, a new modeling technique taking into account the output capacitor effect is proposed for simple dual-phase switched capacitor converters without complex coupling loops. The proposed model employs transient calculation, takes charge redistribution phase into account, and includes the duty cycle, switching frequency as well as output capacitor simultaneously in the final output impedance formula, which enhances accuracy of the model. It is suitable for interleaved and noninterleaved switched capacitor converters. The simulation and experimental results for the unity gain SC converter are provided to verify the proposed theory. [ABSTRACT FROM PUBLISHER]

This paper proposes an individual phase current control (IPCC) method based on optimal zero-sequence current separation for star-connected cascade STATCOMs under unbalanced grid voltage. The IPCC is adopted to get better adaptation to unbalanced conditions. Each cluster of the cascade STATCOM has its own phase current control loop and dc-voltage feedback loop, and it can generate the necessary negative-sequence current automatically to rebalance power. However, the zero-sequence current which is unnecessary and harmful in star configuration is introduced in the process. An optimal zero-sequence current separation is presented to remove the zero-sequence current by reconstructing the reactive current command. This improved IPCC enables star-connected STATCOMs adapt to unbalanced conditions without the need for any power balancing algorithms. Also, the operation range of the proposed control method is analyzed. Simulation research studies are performed to verify the operation range analysis, and the experimental operation is tested on a 25-level ±10 Mvar/10-kV STATCOM product installed at a wind farm. [ABSTRACT FROM PUBLISHER]

Voltage source back-to-back power converters are widely used in grid-tied applications. This paper presents a quasi-centralized direct model predictive control (QC-DMPC) scheme for back-to-back converter control without a dc-link outer-loop controller. Furthermore, the QC-DMPC is experimentally compared with a conventional proportional-integration (PI) dc-link controller-based DMPC (PI-DMPC) scheme. For the QC-DMPC scheme, the dc-link voltage is directly controlled by a grid-side predictive controller using a dynamic reference generation concept and load-side power estimation. For the PI-DMPC scheme, the dc-link voltage is controlled by an external PI controller. Both schemes are implemented on a field programmable gate array (FPGA)-based platform. Effectiveness of the proposed QC-DMPC is verified by both simulation and experimental data. Moreover, FPGA implementation issues (resource usage and timing information), dc-link control performance, and robustness to parameter variation of the two DMPC schemes are compared in detail. The results emphasize that the QC-DMPC may outperform the PI-DMPC scheme in normal operation but with a slightly higher usage of FPGA resources. However, PI-DMPC scheme is more robust when parameter variations are considered. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) is a newly introduced switch-mode converter topology with the potential for high-voltage and high-power applications. This paper focuses on the design and control methods for fault-tolerant operation using redundant submodules (SMs), which is one of the most important features in the MMC topology. By comparing three design schemes of redundant SMs, the most economic and reliable scheme is identified. In addition, a mathematical model of the MMC with arms containing different numbers of SMs is developed. Based on the identified scheme and mathematical model, an energy-balancing control strategy is proposed to keep the MMC operating normally under SM fault conditions. Finally, time-domain simulations of a 61-level MMC system are performed, using the PSCAD/EMTDC software, while experiments are carried out on a 41-level MMC prototype. The simulation and experimental results validate the design scheme, mathematical model, and proposed energy-balancing control strategy. [ABSTRACT FROM AUTHOR]