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This paper proposes for single carrier signaling a simple structure that combines turbo equalization and decoding of correlated sources in multipath-rich multiuser Rayleigh fading multiple access channels (MAC), where the correlation between the sources is exploited by vertical iterations (VI) between the decoders. The bit-flipping model with a flipping probability pe is used to express the correlation ρ between the sources as ρ = 1-2pe. The proposed simple structure, spatially concatenated codes (SpCC), can achieve turbo-like performance over MAC channels suffering from severe inter-symbol interference (ISI), even though it uses short memory convolutional codes. First of all, to achieve turbo-like performance we introduce VIs to exploit the knowledge about the source correlation by exchanging extrinsic log-likelihood ratio (LLR) between the two decoders. We then add a rate-1 doped accumulator (D-ACC) to flexibly adapt for the variation of correlations between the sources. The results of computer simulations and extrinsic information transfer (EXIT) analysis confirm that in multipath-rich environments the proposed structure can achieve excellent performances, 1.02-1.28 dB away from the Slepian-Wolf-Shannon limit, at 1% outage probability for 0 <; ρ ≤ 1. [ABSTRACT FROM PUBLISHER]

Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-transform (LT) code that can be used as rateless error-correcting codes over communication channels. These codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation, which render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, the design of hardware-efficient Raptor decoders with good performance is addressed through joint optimizations targeting 1) the code construction, 2) decoding schedule, and 3) decoder architecture. First, random encoding is decoupled by developing a two-stage LT-code construction scheme that embeds structural features in the LT-graph that are amenable to efficient implementation while guaranteeing good performance. An LT-aware LDPC precode construction methodology that ensures architectural-compatibility with the structured LT code is also proposed. Second, a decoding schedule is optimized to reduce memory cost and account for processing workload-variability caused by the varying code rate. Third, to address the problems of check-degree irregularity and hardware underutilization, a novel reconfigurable check unit that attains a constant throughput while processing a varying number of LT and LDPC nodes is presented. These design steps collectively are employed to generate serial and partially-parallel decoder architectures. A Raptor code instance constructed using the proposed method having LT data-block length of 1210 is shown to outperform or closely match the performance of conventional LDPC codes over the code-rate range [0.4,2\over 3]. The corresponding hardware serial decoder is synthesized using 65-nm CMOS technology and achieves a throughput of 22 Mb/s at rate 0.4 for a BER of 10^-6, dissipates an average power of 222 mW at 1.2 V, and occupies an area of \ 1.77~mm^2. [ABSTRACT FROM AUTHOR]