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Efficient on-chip communication is necessary for exploiting enormous computing power available on a many-core chip. Routing algorithms play a major role for the communication quality and performance of the on-chip interconnection networks. This paper proposes TagNoC, as an on-chip network router architecture with novel hybrid routing approach which reduces latency and power consumption at a fixed cost based on information redundancy. TagNoC is a hybrid routing approach which combines the source and distributed routing methods together. While eliminating packet routing in each router, TagNoC determines the forwarding output port in parallel with input buffering. For a marginal cost increase in header size, as compared to distributed routing techniques, routing latency can be hidden while eliminating power consuming portion of the routing, increasing router throughput and decreasing latency. The proposed TagNoC router is compared to baseline router with distributed routing implementation on a 16-node CMP mesh. Physical implementation of all routers is modeled using synthesized RTL, detailed area analysis, and accurate channel models. Performance evaluation is also carried out utilizing RTL simulation and detailed power analysis on both synthetic and application traffic is performed using post-synthesis gate-level simulation. The simulation results illustrate that TagNoC outperforms as compared to baseline distributed architecture and other source routing methods in terms of power, latency, and throughput. [ABSTRACT FROM AUTHOR]

This paper presents two new ternary operators which can be used in different scrambling crypto algorithms. The employment of the proposed operators ( ScramOp1 and ScramOp2 ) leads to reduction in the number of decoding steps, equivalent to only one operation per digit for the receiver side. These operators are presented for the first time in ternary logic. There are some other ternary operators such as SUM , which are specifically suitable for computer arithmetic but they lack desirable efficiency for cryptographic applications. The transistor-level designs of the operators are simulated by using Synopsys HSPICE with 32 nm bulk-CMOS technology. Simulation results demonstrate that ScramOp1 and ScramOp2 achieve significant saving in energy consumption (2.11% and 12.14%) in comparison with SUM . Additionally, ScramOp2 requires only 52 transistors while 58 and 60 transistors are needed to implement ScramOp1 and SUM , respectively. [ABSTRACT FROM AUTHOR]