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This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature. [ABSTRACT FROM AUTHOR]

With the emergence of the internet-of-things (IoT), many devices process data through the IEEE 802.11 wireless networks. To satisfy the increased data processing, the wireless fidelity (Wi-Fi) networks must have sufficient capacity. IEEE 802.11ax is formulated to provide higher data processing capabilities for IoT applications. The IEEE 802.11ax receiver operating at 5 GHz must be able to withstand interference from nearby IoT applications. Hence, the low-noise amplifier (LNA) employed in such receivers must have a high input-referred third-order intercept point (IIP3). This paper aims to present a wideband LNA operating at 5 GHz with high IIP3 for modern IoT transceivers using IEEE 802.11ax protocol. The LNA is designed and implemented in UMC 65 nm CMOS technology using the Cadence virtuoso design tool. The proposed LNA can provide a maximum gain of 17.64 dB while consuming 8.18 mW of power from a 1.2 V supply. It can be noted that the minimum noise figure (NF) achieved is 3.67 dB and the corresponding IIP3 is 9.44 dBm at 5 GHz from the pre-layout simulations. [ABSTRACT FROM AUTHOR]

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90nm CMOS technology parameters show 41 dBΩ transimpedance gain, 6.5 GHz frequency bandwidth and 2.7 µArms input referred noise, which consumes only 1.67mw power at 1V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver. [ABSTRACT FROM AUTHOR]

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4 GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18 μ m CMOS process. The designed LNA shows a gain of 15.28 dB, NF of 0.376 dB, the power dissipation of 936 μ W and IIP3 of − 4. 3 6 dBm at 2.4 GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3 mW − 1 and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications. [ABSTRACT FROM AUTHOR]

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit analysis. Post-layout simulation results of the proposed clock generator in 180 nm CMOS technology are also presented. It exhibits a wide tuning range of 807 MHz to 2.66 GHz. The phase noise of the output signal is about − 1 1 1 dBc/Hz at 10 MHz offset frequency. Frequency changes less than 1 1 3. 0 6 ppm ∕ ∘ C in the temperature range of − 4 0 ∘ C– 1 0 0 ∘ C. The clock generator consumes 0.657 mW of power. Results show improvement in comparison to the previous works. [ABSTRACT FROM AUTHOR]

A design flow using the / methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, / methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient and the corner frequency , this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GAPF and DEPF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18m CMOS process, but also be migrated to the 0.11m CMOS process, even in the nanometer analog circuit. [ABSTRACT FROM AUTHOR]

As the key component of wireless network-on-chip (WiNoC), wireless router is required to handle a large number of data packets which could cause network congestion. The congestion not only reduces the network performance, but also results in additional power consumption. In this paper, a low-power WiNoC with congestion-aware wireless node is proposed. Firstly, flit counter unit and address resolution unit are added in wireless interface (WI), which can sense the congestion information and destination address information of each wireless node dynamically. Secondly, through the proposed congestion judgment algorithm, the congestion judgment unit in global network can judge the priority of each wireless node pair and set the highest-priority wireless node pair to use the channel resources preferentially. The mechanism can effectively alleviate the congestion of wireless nodes and ensure the stability of system performance. In addition, a sleep mechanism is utilized to switch off WI which fails in the wireless channel competition. Experimental results show that the proposed scheme can effectively improve the performance in terms of packets' transmission latency and network throughput. [ABSTRACT FROM AUTHOR]

To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31W, and the power loss of the entire converter is only 16.53W. [ABSTRACT FROM AUTHOR]

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90nm 1.2V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009, a worst case delay of 858ps, and a power consumption of 898uW at 1G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600) of the total comparator area and contributes 54% (484W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc. [ABSTRACT FROM AUTHOR]

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity. [ABSTRACT FROM AUTHOR]

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit. [ABSTRACT FROM AUTHOR]

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications. [ABSTRACT FROM AUTHOR]

With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software reconfigures the cache to the most energy efficient configuration. EnCache uses dynamic cache reconfiguration and hence, it does not require offline profiling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy e±ciency instead of the LLC energy e±ciency alone. The experiments performed with an ×86-64 simulator and workloads from SPEC2006 suite confirm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system configurations, the average savings in memory subsystem energy over a shared baseline configuration are 30.0% and 27.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz-50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm² × 0.3 mm² using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

With the increasing deployment of Wi-Fi devices in portable embedded systems, the low power design at system level has attracted considerable research attention in the recent past. In this paper, based on hardware features and software architecture of the embedded Wi-Fi devices, we focus on dynamic power management, dynamic frequency scaling, and their influences upon the system power and performance. We propose effective and realizable system power management solution and application modes under various application requirements, such as response, bandwidth, and speed. Experimental results show that the proposed solutions can achieve significant energy savings. [ABSTRACT FROM AUTHOR]

This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented. [ABSTRACT FROM AUTHOR]

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-VP-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage. [ABSTRACT FROM AUTHOR]

In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology. [ABSTRACT FROM AUTHOR]

In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops. [ABSTRACT FROM AUTHOR]