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Modern applications generally need a large volume of computation and communication to fulfill the goal. These applications are often implemented on multiprocessor systems to meet the requirements in computing capacity and communication bandwidth, whereas, how to obtain a good or even the optimal performance on such systems remains a challenge. When tasks of the application are mapped onto different processors for execution, inter-processor communications become inevitable, which delays some tasks' execution and deteriorates the schedule performance. To mitigate the overhead incurred by inter-processor communications and improve the schedule performance, task duplication strategy has been employed in the schedule. Most available techniques for the duplication-based scheduling problem utilize heuristic strategies to produce sub-optimal solutions, however, how to find the optimal duplication-based solution with the minimal schedule makespan remains an unsolved issue. To fill in this gap, this paper proposes a novel Mixed Integer Linear Programming (MILP) formulation for this problem, together with a set of key theorems which enable and simplify the MILP formulation. The proposed MILP formulation can optimize the duplication strategy, serialize the execution of task instances on each processor and determine data precedences among different task instances, thus producing the optimal solution. The proposed method is tested on a set of synthesized applications and platforms and compared with the well-known algorithm. The experimental results demonstrate the effectiveness of the proposed method. • A MILP formulation for the duplication-based scheduling problem is proposed. • A set of optimality theorems are proposed with proof. • The optimality of the proposed method is guaranteed without any premise. • Thorough performance evaluation has been carried out in the paper. [ABSTRACT FROM AUTHOR]

With the rise of cloud service providers and the continuous virtualization of data centers, data center networks are also developing rapidly. As data centers become more and more complex, the demand for security increases dramatically. This paper discusses the privacy inherent in data centers. However, there is no general solution to the privacy problem in data centers due to the device heterogeneity. In this paper, we proposed a local differential privacy-based classification algorithm for data centers. In data mining of data centers, the differential privacy protection mechanism is added to deal with Laplace noise of sensitive information in the pattern mining process. We designed a method to quantify the quality of privacy protection through strict mathematical proof. Experiments demonstrated that the differential privacy-based classification algorithm proposed in this paper has higher iteration efficiency, better security and feasible accuracy. On the premise of ensuring availability, the algorithm has reliable privacy protection characteristics and excellent timeliness. • First, we proposed a local differential privacy-based classification algorithm for data centers. In data mining of data centers, the differential privacy protection mechanism is added to deal with Laplace noise of sensitive information in the pattern mining process. • Second, We proposed a classification algorithm satisfies local differential privacy for cloud computing supported data centers. It can guarantee the validity and reliability of privacy protection and achieves privacy preserving by adding Laplacian mechanism. Experimental results demonstrated that the proposed algorithm has excellent reliability and efficiency. [ABSTRACT FROM AUTHOR]

Within this paper a general-purpose distributed evolutionary algorithm is presented, and is applied to the pair-wise registration of range images. Registration is carried out by utilizing the Grid Closest Point (GCP) for the graphical registration operations and the distributed algorithm to search for the best possible transformation of a scene image that, merged with the model image, yields a 3D reconstruction of the original object. The evolutionary algorithm is a distributed Differential Evolution algorithm that exploits an asynchronous migration mechanism and a multi-population recombination information exchange. Such an algorithm is provided with an adaptive updating scheme based on chaotic features for dynamically updating the control parameters. The scope of the paper is to speed up the registration process by using processor specialized to handle graphical operations and multi-core platforms. On the one hand, we investigate the use of either Graphic Processing Units (GPUs) or multi-core architectures to lower the execution time of the GCP procedure. On the other hand, we evaluate the performance of the distributed evolutionary algorithm in terms of solution quality by examining different multi-core architectures. Experimental results on a set of publicly available images show that, to perform the GCP, reductions in the execution times by one order of magnitude are obtained by harnessing the computational power of GPU and multi-core platforms with respect to the execution on a CPU-based framework. Furthermore, a comparison with the state-of-the-art sequential evolutionary algorithm for range image registration reveals that the adaptive distributed Differential Evolution algorithm allows attaining integral 3D models from 3D scan datasets that are better in terms of both quality and robustness. • GPU and multi-core Differential Evolution are used for range image registration. • The proposed algorithm is endowed with features of adaptivity and chaos. • The approach has been compared against the best performing algorithm. • The results show one order of magnitude reductions in terms of execution time. [ABSTRACT FROM AUTHOR]

This paper describes a unified view of parallel evolutionary algorithms for multi-objective optimization problems. The parallel optimization algorithms are detailed from both design and implementation aspects. The proposed taxonomy is based on three hierarchical parallel models. Moreover, various parallel architectures are taken into account. The performance assessment issue of parallel multi-objective evolutionary algorithms (MOEA) is also presented. This work can be extended to any population-based metaheuristics such as particle swarm and scatter search. • The main highlights of this paper is the development of a unified view of parallel multi-objective evolutionary algorithms in terms of design and implementation. • The parallel models have been analyzed according to different parallel architectures. • The different parallel models have been illustrated. • The paper is also a guideline to researchers and engineers to design and implement efficient and effective parallel evolutionary algorithms for multi-objective optimization. [ABSTRACT FROM AUTHOR]

This paper describes LFRic: the new weather and climate modelling system being developed by the UK Met Office to replace the existing Unified Model in preparation for exascale computing in the 2020s. LFRic uses the GungHo dynamical core and runs on a semi-structured cubed-sphere mesh. The design of the supporting infrastructure follows object-oriented principles to facilitate modularity and the use of external libraries where possible. In particular, a 'separation of concerns' between the science code and parallel code is imposed to promote performance portability. An application called PSyclone, developed at the STFC Hartree centre, can generate the parallel code enabling deployment of a single source science code onto different machine architectures. This paper provides an overview of the scientific requirement, the design of the software infrastructure, and examples of PSyclone usage. Preliminary performance results show strong scaling and an indication that hybrid MPI/OpenMP performs better than pure MPI. • A new dynamical core and software infrastructure for weather and climate modelling. • Mixed finite element formulation on an unstructured mesh facilitates scalability. • A separation of concerns between domain and computational science. • Use of a Domain Specific Language and automatic code parallelism. • Modular design facilitating use of community libraries and frameworks. • Utilises object-orientated functionality of Fortran 2003. [ABSTRACT FROM AUTHOR]

This paper presents INRFlow, a mature, frugal, flow-level simulation framework for modelling large-scale networks and computing systems. INRFlow is designed to carry out performance-related studies of interconnection networks for both high performance computing systems and datacentres. It features a completely modular design in which adding new topologies, routings or traffic models requires minimum effort. Moreover, INRFlow includes two different simulation engines: a static engine that is able to scale to tens of millions of nodes and a dynamic one that captures temporal and causal relationships to provide more realistic simulations. We will describe the main aspects of the simulator, including system models, traffic models and the large variety of topologies and routings implemented so far. We conclude the paper with a case study that analyses the scalability of several typical topologies. INRFlow has been used to conduct a variety of studies including evaluation of novel topologies and routings (both in the context of graph theory and optimization), analysis of storage and bandwidth allocation strategies and understanding of interferences between application and storage traffic. • We present our flow-level simulation framework INRFlow. • It is a mature, flexible and efficient tool for simulating large scale systems. • It models network, storage, scheduler and applications. • It has been used extensively for our research in the past. • INRFlow is open source and programmed in C. [ABSTRACT FROM AUTHOR]

With the advent of die stacking technology and big data applications, Processing-in-memory (PIM) is regaining attention as a promising technology for improving performance and energy efficiency. Although various PIM techniques have been proposed in recent studies for effectively offloading computation from the host, the thermal impacts of PIM offloading have not been fully explored. This paper investigates the thermal constraints of PIM and proposes techniques to enable thermal awareness for efficient PIM offloading. To understand the thermal effects of 3D-stacked designs, we measure the temperature of a real Hybrid Memory Cube (HMC) prototype and observe that compared to conventional DRAM, HMC reaches a significantly higher operating temperature, which causes thermal shutdowns with a passive cooling solution. Even with a commodity-server cooling solution, when in-memory processing is highly utilized, HMC fails to maintain the temperature of the memory dies within the normal operating range. In this paper, we propose a collection of software- and hardware-based techniques to enable thermal-aware PIM offloading by controlling the intensity of PIM offloading at runtime. Our evaluation results show that the proposed techniques achieve up to 1.4 × and 1.37 × speedups compared to non-offloading and naïve offloading scenarios. • We provide a thermal analysis to understand the thermal constraints of a real-world 3D memory. • Our thermal analysis shows that DRAM layers can exceed the normal operating temperature when PIM offloading is used. • We propose a collection of thermal-aware source throttling techniques that dynamically controls the intensity of PIM offloading. [ABSTRACT FROM AUTHOR]

Finding a novel drug is a very long and complex procedure. Using computer simulations, it is possible to accelerate the preliminary phases by performing a virtual screening that filters a large set of drug candidates to a manageable number. This paper presents the implementations and comparative analysis of two GPU-optimized implementations of a virtual screening algorithm targeting novel GPU architectures. This work focuses on the analysis of parallel computation patterns and their mapping onto the target architecture. The first method adopts a traditional approach that spreads the computation for a single molecule across the entire GPU. The second uses a novel batched approach that exploits the parallel architecture of the GPU to evaluate more molecules in parallel. Experimental results showed a different behavior depending on the size of the database to be screened, either reaching a performance plateau sooner or having a more extended initial transient period to achieve a higher throughput (up to 5x), which is more suitable for extreme-scale virtual screening campaigns. • Analyze and compare two CUDA implementations of a real-world virtual screening application with a completely different design. • Experimental results show how a batched approach yields a much higher throughput than an approach that spreads the computation across the GPU. • To explain the performance, we performed a detailed analysis considering the algorithm, hardware characteristics, and input features. [ABSTRACT FROM AUTHOR]

Many applications need to execute Single-Source Shortest Paths (SSSP) algorithm on each snapshot of a time-evolving graph, leading to long waiting times experienced by the users of such applications. However, these applications are often time-sensitive, the delayed computation results can lead to the loss of best decision-making opportunities. To address this problem, in this paper we propose an efficient SSSP algorithm for time-evolving graphs, called V-Grouper. The main idea of V-Grouper is to avoid the redundant computations of the same vertex in different snapshots. Our experimental results over real-world time-evolving graphs show that, due to the high similarity of consecutive snapshots, the computation results of one vertex in neighboring snapshots are equal with a high probability. At the beginning of computation, V-Grouper first divides all the versions of a given vertex in different snapshots into vertex groups, where the computation result of each version is predicted based on the aforementioned insight of neighboring snapshots having equal results. The versions of the vertex in each group have the same predicted computation result. During the computation process for each vertex group, only one version needs to participate in computation, avoiding a large number of redundant computations. Experimental results show that V-Grouper is up to 64.31× faster than the state-of-the-art SSSP algorithm. • An efficient algorithm to compute SSSPs of the snapshots of time-evolving graph. • A compact data structure of time-evolving graph to save the memory space and improve the snapshot access speed. • An effective design to speed up the interactions between vertex groups.An effective design to speed up the interactions between vertex groups. [ABSTRACT FROM AUTHOR]

It has been shown that any nonblocking algorithm for work-stealing in the standard asynchronous shared memory model of computation must use expensive Read-After-Write synchronization patterns or atomic Read-Modify-Write instructions. Algorithms for relaxations of work-stealing have been proposed, which only partially avoid this impossibility result. In restricted models of computation, work-stealing algorithms have been designed that avoid Read-After-Write patterns and atomic Read-Modify-Write instructions. This paper considers work-stealing with multiplicity , a relaxation in which every task is taken by at least one process, and any process can take any task at most once. We study two variants of the relaxation, for each variant designing a Read / Write wait-free algorithm in the standard asynchronous shared memory model. The two algorithms are devoid of Read-After-Write synchronization patterns in all their operations, and additionally, the algorithm for the second variant has constant step complexity and is fence-free. Namely, no specific ordering among the algorithm's instructions is required beyond what is implied by data dependence. To our knowledge, these are the first algorithms for relaxations of work-stealing possessing all these properties. The algorithms are also solutions to relaxed versions of single-enqueuer multi-dequeuer queues. The theoretical results are complemented with an experimental evaluation showing that the benefits of relaxed work-stealing vary depending on the application, concretely on the complexity of the work associated with each task. • We present two asynchronous work-stealing algorithms with relaxation, work-stealing with multiplicity and weak-multiplicity. • In the first one, tasks are taken by at least one operation and if taken by several operations, they must be pairwise concurrent. • In the second one, Take/Steal operations extracting the same task may not be concurrent, however, each process extracts tasks at most once. • The algorithms are wait-free, read/write, and devoid of read-after-write synchronization patterns. • The proposed algorithms outperform standard work-stealing algorithms and exhibit similar or better performance than known relaxed algorithms in some practical settings. [ABSTRACT FROM AUTHOR]

Distributed Systems are often composed of geographically separated components, where the clocks may not be perfectly synchronized. As such verifying the correctness of such system properties are a major challenge and are of utmost importance. In this paper, we describe a centralized runtime monitoring technique for distributed system. First, we propose a generalized runtime verification technique for verifying partially synchronous distributed computations for the metric temporal logic (MTL) by exploiting bounded-skew clock synchronization. Second, we introduce a progression-based formula rewriting scheme for monitoring MTL specifications which employs SMT solving techniques and report experimental results. Third, we also quantify each event according to the possible time of occurrence and calculate the probabilistic guarantee for generating the verification verdict. Lastly, we have implemented the entire procedure and report on extensive synthetic experimental results using UPPAAL, a set of cross-chain transactions implemented on Ethereum and an Industrial Control System of a water treatment plant. • Runtime Verification of partially-synchronous distributed systems. • Introduce a progression-based rewriting scheme for MTL specifications. • Calculate the probabilistic guarantee for generating verification verdict. • Case study includes cross-chain transactions on Ethereum. [ABSTRACT FROM AUTHOR]

Sparse matrix-vector multiplication (SpMV) optimization on GPUs has been challenging due to irregular memory accesses and unbalanced workloads. The majority of existing solutions assign a fixed number of threads to one or more rows of sparse matrices according to empirical formulas. However, this method does not give the optimal thread configuration and results in a significant performance loss. This paper proposes a new machine learning-based thread assignment strategy for SpMV on GPU, predicting the near-optimal thread configuration for matrices. Further, we partition irregular sparse matrices into blocks according to the distribution of non-zero elements and predict the optimal thread configuration for each block. A new SpMV kernel is designed to accelerate the execution of different blocks. Experimental results show that our machine learning-based approach can select the near-optimal thread configuration for most matrices. The efficiency of SpMV for irregular matrices is also improved by matrix partitioning and blockwise prediction. Finally, we dive into the trained model to find out the connection between the features of a sparse matrix and its optimal thread configuration. • We present a detailed and deep discussion on two popular CSR-based SpMV algorithms. • A ML-based thread configuration method for SpMV on GPU is proposed. • We propose a non-zero element distribution-aware thread configuration scheme. • Extensive performance comparisons to existing SpMV algorithms on GPU are provided. • We present a deep analysis of the trained ML model and its overhead. [ABSTRACT FROM AUTHOR]

• Design of a smart low-cost energy meter as an internet of energy (IoE) device. • How to measure energy performance on distributed and heterogeneous computers. • Energy consumption in parallel programming must be considered as a design parameter. This paper presents the design and implementation of a low-cost system oriented to the synchronised and real-time surveillance and monitoring of electrical parameters of different computer devices. To measure energy consumption in a computer system, it is proposed to use, instead of a general-purpose wattmeter, one designed ad-hoc and synchronously collects the energy consumption of its various nodes or devices. The implementation of the devised system is based on the confluence of several technologies or tools widely used in the Internet of Things. Thus, this article the intelligent objects are the power meters, whose connections are based on the low-cost ESP32 microcontroller. The message transmission between devices is carried out with the standard message queuing telemetry transport (MQTT) protocol, the measurements are grouped in a database on an InfluxDB server that store the sensor data as time series, and Grafana is used as a graphical user interface. The efficiency of the proposed energy monitoring system is demonstrated by the experimental results of a real application that successfully and synchronously records the voltage, current, active power and cumulative energy consumption of a distributed cluster that includes a total of 60 cores. [ABSTRACT FROM AUTHOR]

Transportation Problem (TP) is a popular linear program for optimally matching several supply centers to several demand centers at the smallest transportation cost. Recent disruptions in the physical supply chains and the growth of internet marketplaces such as ride-sharing, doorstep delivery, and expedited shipping have engendered a need for efficient algorithms to solve large-scale TPs in near real-time. The Transportation Simplex Algorithm (TSA) is a traditional method to solve TP to optimality. However, TSA is unsuitable for these new applications because of its long run time. The evolution of accelerated computing using Graphics Processing Units (GPUs) has recently attracted some interest in solving optimization problems. In this paper, we develop a GPU-accelerated TSA for large-dimensions. The underlying parallelism in the iterative steps of TSA has been uncovered and exploited. The results show that the accelerated algorithm performs up to 8 times faster on average compared to the known sequential algorithm and up to 4 times faster on average compared to the state-of-the-art commercial Linear Programming solver. • Transportation Problem is a fundamental problem in operations research. • Transportation Simplex Algorithm has been accelerated on a GPU. • Creative parallelism in the iterative steps has been uncovered and exploited. • Large problems with 1000 supply and 10,000 demand nodes can be solved. • It is 4x faster than a leading LP solver and 8x faster than sequential counterpart. [ABSTRACT FROM AUTHOR]

Many emerging applications analyze data streams by running graphs of communicating tasks called operators. To develop and deploy such applications, Stream Processing Systems (SPSs) like Apache Storm and Flink have been made available to researchers and practitioners. They exhibit imperative or declarative programming interfaces to develop operators running arbitrary algorithms working on structured or unstructured data streams. In this context, the interest in leveraging hardware acceleration with GPUs has become more pronounced in high-throughput use cases. Unfortunately, GPU acceleration has been studied for relational operators working on structured streams only, while non-relational operators have often been overlooked. This paper presents WindFlow , a library supporting the seamless GPU offloading of general partitioned-stateful operators, extending the range of operators that benefit from hardware acceleration. Its design provides high throughput still exposing a high-level API to users compared with the raw utilization of GPUs in Apache Flink. • Data Stream Processing on Heterogeneous Systems. • Efficient use of System-on-Chip devices for stream processing workloads. • CUDA kernels supporting partitioned-stateful streaming operators on GPU. • High-level API to express CPU+GPU streaming applications in C++. [ABSTRACT FROM AUTHOR]

Atomic Broadcast is an essential broadcast primitive as it ensures the consistency of distributed replicas. However, it is notoriously non-scalable. In this work, we introduce the Leaderless Hierarchical Atomic Broadcast (LHABcast) algorithm, which has two properties to improve scalability. First, it is a fully decentralized algorithm that does not rely on a sequencer/leader, which is often a significant bottleneck. Processes running LHABcast send messages with local sequence numbers and order messages received from other processes using timestamps inspired on Lamport's logical clocks. A process that receives the required set of timestamps can make a decision about the overall sequence of message delivery. Second, the algorithm is hierarchical: processes are organized on a vCube logical overlay network, which has several logarithmic properties and allows the construction of autonomous spanning trees. vCube also works as a failure detector, assuming crash faults and an asynchronous system model. In this paper, LHABcast is described, specified, and proven to be correct. Both simulation and experimental results are presented. A comparison with an all-to-all strategy shows that the number of messages sent by LHABcast is significantly lower in both fault-free and faulty scenarios. An implementation of LHABcast in Akka.io achieved up to 3.9 times higher throughput in fault-free scenarios than an implementation of the Raft-based Apache Ratis. • LHABcast is a fully decentralized leaderless algorithm broadcast algorithm. • LHABcast organizes processes on a vCube, which has several logarithmic properties. • LHABcast uses autonomic spanning trees rooted at the sender for message dissemination. • LHABcast is described with examples, and multiple properties are proved. • LHABcast was evaluated both with a Neko simulation and using the Java Akka framework. [ABSTRACT FROM AUTHOR]

Resource scheduling plays a vital role in High-Performance Computing (HPC) systems. Most scheduling research in HPC has focused on only a single type of resource (e.g., computing cores or I/O resource). With the advancement in hardware architectures and the increase in data-intensive HPC applications, there is a need to simultaneously consider a diverse set of resources (e.g., computing cores, cache, memory, I/O, and network resources) in the design of runtime schedulers for improving the overall application performance. In this paper, we study multi-resource scheduling to minimize the makespan of computational workflows comprised of moldable parallel jobs. Moldable jobs allow the scheduler to flexibly select a variable set of resources before execution, thus can adapt to the available system resources (as compared to rigid jobs) while staying easy to design and implement (as compared to malleable jobs). We propose a Multi-Resource Scheduling Algorithm (MRSA), which combines a novel resource allocation strategy and an extended list scheduling scheme to schedule the jobs. We prove that, on a system with d types of schedulable resources, MRSA achieves an approximation ratio of 1.619 d + 2.545 d + 1 for any d ≥ 1 , and a ratio of d + 3 d 2 3 + O (d 3) when d is large (i.e., d ≥ 22). We also present improved approximation results for workflows comprised of jobs with special precedence constraints (e.g., series-parallel graphs, trees, and independent jobs). Further, we prove a lower bound of d on the approximation ratio of any list-based scheduling algorithm with local priority considerations. Finally, we conduct a comprehensive set of simulations to evaluate the performance of the algorithm using synthetic workflows of different structures and moldable jobs following different speedup models. The results show that MRSA fares better than the theoretical bound predicts, and that it consistently outperforms two baseline heuristics under a variety of parameter settings, illustrating its robust practical performance. • We consider a multi-resource scheduling problem for moldable jobs with precedence constraints. • We propose a multi-resource scheduling algorithm (MRSA) for the studied problem. • We prove several approximation results of MRSA for general graphs and some special graphs. • We conduct simulations to evaluate the performance of MRSA under variety of settings. [ABSTRACT FROM AUTHOR]

This paper presents a method for detecting cyber-attacks in cyber-physical systems using a monitor. The method employs an abstract model called Tiny Twin, which is built at design time and is used at runtime to detect inconsistencies. Tiny Twin is a state transition system that represents the observable behavior of the system from the monitor point of view. We model the behavior of the system in the Rebeca modeling language and use Afra model checker to generate the state space. The Tiny Twin is built automatically, by abstracting the state space while keeping the observable actions and preserving the trace equivalence. For doing that we had to solve the complexities in the state space introduced by time-shifts, nondeterministic assignments and abstraction of internal actions. We formally define the state space as Concise Rebeca Timed Transition System (CRTTS), and then map CRTTS to an LTS. The LTS is then fed to a tool to abstract away the non-observable actions. • Propose a mapping to create Tiny Twin based on a Timed Rebeca model. • Detect cyber-attacks using Tiny Twin. • Formally define Concise Rebeca Timed Transition System (CRTTS). • Develop ltscast function to map CRTTS to an LTS. • Preserve trace equivalence using mCRL2 ltsconvert tool. [ABSTRACT FROM AUTHOR]

Synchronous SGD with data parallelism, the most popular parallelization strategy for CNN training, suffers from the expensive communication cost of averaging gradients among all workers. The iterative parameter updates of SGD cause frequent communications and it becomes the performance bottleneck. In this paper, we propose a lazy parameter update algorithm that adaptively adjusts the parameter update frequency to address the expensive communication cost issue. Our algorithm accumulates the gradients if the difference of the accumulated gradients and the latest gradients is sufficiently small. The less frequent parameter updates reduce the per-iteration communication cost while maintaining the model accuracy. Our experimental results demonstrate that the lazy update method remarkably improves the scalability while maintaining the model accuracy. For ResNet50 training on ImageNet, the proposed algorithm achieves a significantly higher speedup (739.6 on 2048 Cori KNL nodes) as compared to the vanilla synchronous SGD (276.6) while the model accuracy is almost not affected (<0.2% difference). • Adaptive parameter update frequency control for scalable parallel deep learning. • Allowing gradient accumulation considering the direction of the gradients. • Reducing per-iteration communication cost at the input side model layers. • Overlapping gradient communications with backpropagation computations. [ABSTRACT FROM AUTHOR]

• Limited power of randomization in dealing with adaptive adversaries. • Derandomizing algorithms via simulation. • Simulating a dynamic network on top of another dynamic network. This paper investigates the power of randomization in general distributed algorithms in dynamic networks where the network's topology may evolve over time, as determined by some adaptive adversary. In such a context, randomization may help algorithms to better deal with i) "bad" inputs to the algorithm, and ii) evolving topologies generated by "bad" adaptive adversaries. We prove that randomness offers limited power to better deal with "bad" adaptive adversary. We define a simple notion of prophetic adversary for determining the evolving topologies. Such an adversary accurately predicts all randomness in the algorithm beforehand, and hence the randomness will be useless against "bad" prophetic adversaries. Given a randomized algorithm P whose time complexity satisfies some mild conditions, we prove that P can always be converted to a new algorithm Q with comparable time complexity, even when Q runs against prophetic adversaries. This implies that the benefit of P using randomness for dealing with the adaptive adversaries is limited. [ABSTRACT FROM AUTHOR]

• Model: Proposed a new model to handle different SLAs of workloads and guarantee the worst-case delay of delay-tolerant workload. • Algorithm: Designed an O (1) time online control algorithm OSDG for each slot to achieve the long term optimization objective. • Analysis and Experiment: Proved our algorithm achieves an explicit [ O (1 / V) , O (V) ] cost-delay tradeoff and validated its performance. More and more cloud data centers are turning to leverage on-site renewable energy to reduce power cost for sustainable development. But how to effectively coordinate the intermittent renewable energy with workload remains to be a great challenge. This paper investigates the problem of workload scheduling for power cost minimization under the constraints of different Service Level Agreements (SLAs) of delay tolerant workload and delay sensitive workload for green data centers in a smart grid. Different from the existing studies, we take into consideration of the impact of zero price in the smart grid and the cost of on-site renewable energy. To handle the randomness of workload, electricity price and renewable energy availability, we first formulate the problem as a constrained stochastic problem. Then we propose an efficient online control algorithm named ODGWS (Online Delay-Guaranteed Workload Scheduling) which makes online scheduling decisions achieve a bounded guarantee from the worst scheduling delay for delay tolerant workload. Compared with the existing solutions, our ODGWS decomposes the problem into that of solving a simple optimization problem within each time slot in O (1) time without needing any future information. The rigorous theoretical analysis demonstrates that our algorithm achieves a [ O (1 V) , O (V) ] cost-delay tradeoff, where V is a balance parameter between the cost optimality and service quality. Extensive simulations based on real-world traces are done to evaluate the performance of our algorithm. The results show that ODGWS saves about 5% average power cost compared with the baseline algorithms. [ABSTRACT FROM AUTHOR]

The popularity of blockchain platforms and their applications in industry and academia keeps rising. The multifarious requirements stimulate another technique, graph data and algorithms, to join the blockchains; thus, studies, scenarios, and solutions about graph-related blockchains have emerged. This paper aims to see whether the state-of-the-art studies satisfy the applications through a comprehensive survey on graph-related blockchains. To answer why a blockchain needs graphs in general, we analyze literature about blockchain and graph, as well as use cases on the application-oriented and graph-related scenarios collected from practical blockchain projects. The paper summarizes three graph-related blockchain studies: graph algorithms for blockchains, graph data in blockchains, and graph applications on blockchains. Based on these summarization, it figures out the gaps between the studies and the applications, that is, few of studies natively integrate graph computing into a blockchain. Here, the "graph integration" means processing on-chain graph data, which contains blockchain information, in a real-time, distributed, and consensual manner. We propose the prospect of the Graph-integrated Blockchain Platform (GiBP for short), and explain why a GiBP is inevitable, the challenges of a GiBP, and the GiBPs' main functions and features people expect for future research. • Summarize and classify prior works on existing graph-related blockchains. • Summarize and refine prior works on graph-related blockchains. • Draw the gaps between the studies and the applications of graph-related blockchain. • Propose the prospect of the Graph-integrated Blockchain Platform (GiBP for short). [ABSTRACT FROM AUTHOR]

In the existing literature of the Mutual Visibility problem for autonomous robot swarms, the adopted visibility models have some idealistic assumptions that are not consistent with practical sensing device implementations. This paper investigates the problem in the more realistic visibility model called opaque fat robots with slim omnidirectional camera. The robots are modeled as unit disks, each having an omnidirectional camera represented as a disk of smaller size. The region obstructed by a single robot in this model is a truncated infinite cone. This makes the visibility model significantly challenging compared to the previous ones. We assume that the robots have compasses that allow agreement in the direction and orientation of both axes of their local coordinate systems. The robots are equipped with visible lights which serve as a medium of communication and also as a form of memory. We present a distributed algorithm for the Mutual Visibility problem which is provably correct in the semi-synchronous setting. Our algorithm also provides a solution for Leader Election which we use as a subroutine in our main algorithm. Although Leader Election is trivial with two axis agreement in the full visibility model, it is challenging in our case and is of independent interest. • First paper to study mutual visibility for fat robots with slim omnidirectional camera. • Each robot modeled as a unit disk with camera represented as a disk of smaller size. • Algorithms for mutual visibility and leader election in semi-synchronous setting. • Extensive simulation studies assessing the algorithms under various performance metrics. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is an information carrier based on the Internet and traditional telecommunications network, which enables all ordinary physical objects that can be independently addressed to form an interconnected network. User authentication protocol is an essential technology for security and privacy in the IoT environment. This paper analyzes the security of Mirsaraei et al.'s three-factor authentication scheme for IoT environments (Mirsaraei et al., 2022 [31]), and finds that the scheme cannot provide users with untraceability, perfect forward secrecy or the resistance of key compromise impersonation attack. The article improves Mirsaraei et al.'s scheme and proposes a three-factor authentication protocol with perfect forward secrecy using elliptic curve cryptosystem, which retains the general process of Mirsaraei et al.'s scheme. The formal security analysis of the proposed protocol is carried out by ROR (Real-or-Random) model, and the formal security verification of the proposed protocol is implemented by Proverif tool. The cryptoanalysis results demonstrate that the proposed protocol makes up for the shortcomings of Mirsaraei et al.'s scheme in security and can resist more malicious attacks as opposed to recent schemes. Moreover, the performance analysis using MIRACL (Multiprecision Integer and Rational Arithmetic C/C++ Library) shows that, the proposed protocol has great advantages over analogical three-factor authentication schemes in terms of computational overhead and communication overhead. • This paper find the security defects of Mirsaraei et al.'s scheme and improve it. • The proposed scheme provides excellent computational and communication cost. • The proposed scheme provides perfect forward secrecy. • Formal security analyses demonstrate the security of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper explores Google's Edge TPU for implementing a practical network intrusion detection system (NIDS) at the edge of IoT, based on a deep learning approach. While a significant number of related works explore machine learning-based NIDS for the IoT edge, they generally lack considering the issue of the required computational and energy resources. The focus of this paper is the exploration of deep learning-based NIDS at the edge of IoT, and in particular, the computational and energy efficiency. In particular, the paper studies Google's Edge TPU as a hardware platform and considers the following three key metrics: computation (inference) time, energy efficiency and traffic classification performance. Various scaled model sizes of two major deep neural network architectures are used to investigate these three metrics. The performance of the Edge TPU-based implementation is compared with that of an energy-efficient embedded CPU (quad-core ARM Cortex-A53). • This is the first paper that explores Edge TPU for NIDS in IoT, to the best of our knowledge. • This paper investigates various feed-forward and convolutional neural network structures, with different hyperparameters, on Edge TPU and the quad-core ARM cortex-A53 hardware platforms. • The performance is compared on the hardware platforms, across multiple performance metrics including the attack detection/classification performance, the inference time, and energy efficiency. • This study evaluated the energy efficiency of explored neural network structures versus the model size on Edge TPU and Cortex-A53 platforms. [ABSTRACT FROM AUTHOR]

• The EasyPAP environment allows students to really focus on parallelism while developing OpenMP, OpenCL or MPI kernels. • Interactive display of increasingly optimized variants of a 2D kernel help to popularize HPC. • Linking CPUs and image tiles in monitoring windows allow to better understand scheduling policies. • Linking tasks and image tiles when visualizing port mortem execution traces help to diagnose parallel efficiency issues. This paper presents EasyPAP , an easy-to-use programming environment designed to help students to learn parallel programming. EasyPAP features a wide range of 2D computation kernels that the students are invited to parallelize using Pthreads, OpenMP, OpenCL or MPI. Execution of kernels can be interactively visualized, and powerful monitoring tools allow students to observe both the scheduling of computations and the assignment of 2D tiles to threads/processes. By focusing on algorithms and data distribution, students can experiment with diverse code variants and tune multiple parameters, resulting in richer problem exploration and faster progress towards efficient solutions. We present selected lab assignments which illustrate how EasyPAP improves the way students explore parallel programming. [ABSTRACT FROM AUTHOR]

• Improved distributed approximation for Steiner tree. • Approximation algorithms for Steiner tree in the CONGEST model of distributed computing. • Steiner tree problem in network optimization. In this paper we present two deterministic distributed algorithms for the Steiner tree (ST) problem in the CONGEST model. The first algorithm computes a 2 (1 − 1 / ℓ) -approximate ST using O (S + n log ⁎ ⁡ n) rounds and O (m S + n 3 / 2) messages for a graph of n nodes and m edges, where S is the shortest path diameter of the graph and ℓ is the number of leaf nodes in the optimal ST. It improves the round complexity of the best distributed ST algorithm known so far, which is O ˜ (S + min { S t , n }) [34] , where t is the number of terminal nodes. The second algorithm improves the message complexity of the first one by dropping the additive term of O (n 3 / 2) at the expense of a logarithmic multiplicative factor in the round complexity. We also show that for graphs with S = O (log ⁡ n) , a 2 (1 − 1 / ℓ) -approximate ST can be deterministically computed using O ˜ (n) rounds and O ˜ (m) messages and these complexities almost coincide with the results of some of the singularly-optimal minimum spanning tree (MST) algorithms proposed in [15,22,37]. [ABSTRACT FROM AUTHOR]

• Propose the aligned storage formats ACSR and AELL. • Put forward a parallel SpMV algorithm based on ACSR and AELL formats. • Theoretically analyze the performance of SpMV on ARM processors. • Evaluate the performance of our optimization on Kunpeng 920 processors. Sparse matrix-vector multiplication (SpMV) has always been a hot topic of research for scientific computing and big data processing, but the sparsity and discontinuity of the nonzero elements in a sparse matrix lead to the memory bottleneck of SpMV. In this paper, we propose aligned CSR (ACSR) and aligned ELL (AELL) formats and a parallel SpMV algorithm to utilize NEON SIMD registers on ARM processors. We analyze the impact of SIMD instruction latency, cache access, and cache misses on SpMV with different formats. In the experiments, our SpMV algorithm based on ACSR achieves 1.18x and 1.56x speedup over SpMV based on CSR and SpMV in PETSc, respectively, and AELL achieves 1.21x speedup over ELL. The deviations between the theoretical results and experimental results in the instruction latency and cache access are 10.26% and 10.51% in ACSR and 5.68% and 2.91% in AELL, respectively. [ABSTRACT FROM AUTHOR]

• Multi-GPU and Unified Memory implementation of the Multi-Zone NAS Benchmarks. • Analysis of the programmability and performance effects of Unified Memory. • Unified Memory and per-GPU allocation have similar programming efforts. • Unified-Memory version outperforms manual allocation from 1.1x to 1.85x. GPU-based computing systems have become a widely accepted solution for the high-performance-computing (HPC) domain. GPUs have shown highly competitive performance-per-watt ratios and can exploit an astonishing level of parallelism. However, exploiting the peak performance of such devices is a challenge, mainly due to the combination of two essential aspects of multi-GPU execution: memory allocation and work distribution. Memory allocation determines the data mapping to GPUs, and therefore conditions all work distribution schemes and communication phases in the application. Unified Virtual Memory simplifies the codification of memory allocations, but its effects on performance depend on how data is used by the devices and how the devices' driver is going to orchestrate the data transfers across the system. In this paper we present a multi-GPU and Unified Virtual Memory (UM) implementation of the NAS Multi-Zone Parallel Benchmarks which alternate communication and computation phases offering opportunities to overlap these phases. We analyse the programmability and performance effects of the introduction of the UM support. Our experience shows that the programming efforts for introducing UM are similar to those of having a memory allocation per GPU. On an evaluation environment composed of 2 x IBM Power9 8335-GTH and 4 x GPU NVIDIA V100 (Volta), our UM-based parallelization outperforms the manual memory allocation versions by 1.10x to 1.85x. However, these improvements are highly sensitive to the information forwarded to the devices' driver describing the most convenient location for specific memory regions. We analyse these improvements in terms of the relationship between the computational and communication phases of the applications. [ABSTRACT FROM AUTHOR]

Failure detectors (FD)s are celebrated for their modularity in solving distributed problems. Algorithms are constructed using FD building blocks. Synchrony assumptions to implement FDs are studied separately and are typically expressed as eventual guarantees that need to hold, after some point in time, forever and deterministically. But in practice, they may hold only probabilistically and temporarily. This paper studies FDs in a realistic system N , where asynchrony is inflicted by probabilistic synchronous communication. We first address a problem with ⋄ S , the weakest FD to solve consensus: an implementation of "consensus with probability 1" is possible in N without randomness in the algorithm, while an implementation of " ⋄ S with probability 1" is impossible in N. We introduce ⋄ S ⁎ , a new FD with probabilistic and temporal accuracy. We prove that ⋄ S ⁎ (i) is implementable in N and (ii) can replace ⋄ S , in several existing deterministic consensus algorithms that use ⋄ S , to yield an algorithm that solves "consensus with probability 1". We extend our results to other FD classes, e.g., ⋄ P , and to a larger set of problems (beyond consensus), which we call decisive problems. • We propose a way to preserve the usefulness of failure detectors (FD)s as software building blocks in probabilistically synchronous systems as (N). • We define <>S*, a probabilistic FD with accuracy ensured for arbitrarily long finite periods and that can be implemented in systems as N. • We present an optimal <>S* algorithm, which achieves in the best case the lowest communication overhead (C-1) compared to all known <>S algorithms. • We extend our FD definitions for other FD classes and other distributed computing problems besides consensus, which we call decisive problems. • We encapsulate the randomization of probabilistic links in the very abstraction of FD, without affecting deterministic algorithms built on top. [ABSTRACT FROM AUTHOR]

Cloud resources provide various categories of (VM) virtual machine requests which is assigned with clients for an exact timespan. Currently, the method of VM scheduling within the Cloud environment is decided by a fixed-price scheduling algorithm, during which the user pays a fixed amount per unit time so as to obtain the resources. However, such a scheduling algorithm is not effective for Cloud even though the Cloud resources are dynamically allocated and released. To address this issue, the adaptive scheduling algorithm called as Dynamic pricing based Combinatorial Auction allocation mechanism is proposed. It will be used to increase the resource utilization as well as user satisfaction through dynamic pricing with the combinatorial auction. Our proposed market-based scheduling algorithm uses the principle of auction mechanism for the purpose of extends the satisfaction of Cloud suppliers and clients. This technique reconstructs the current preferences of resource allotment so as to allot resources in advance for emergent virtual machine demands. Then Collective-target augmentation numerical prototype is demonstrated, which forms the minimal execution equivalent range connecting physical machines with virtual machines, and the objective of resource allotment is to obtain minimal quantity of physical machines. The simulation experimental outcomes express that the proposed scheduling methodology and Collective-target augmentation numerical prototypes are capable to adequately increase the quality of service (QoS), improves profit of suppliers and resource utilization. • In our paper, we proposed Dynamic pricing with combinatorial action mechanism to get efficient performance. • Our DPCAM provides higher user satisfaction. • It increases resource utilization rate. • Using our scheme all the providers may get a chance to win an auction. • So that quality of service can be achieved. [ABSTRACT FROM AUTHOR]

• Heterogeneous parallel computing is rarely taught in required undergraduate courses. • Concepts of heterogeneous computing can be taught even in CS1 and CS2. • Pollack's Rule and Amdahl's Law help motivate the shift to heterogeneous processors. • Using ARM processors, an instructor can show a low-power mode and SIMD operations. Heterogeneous architectures have emerged as a dominant platform, not only in high-performance computing but also in mobile processing, cloud computing, and the Internet of Things (IoTs). Because the undergraduate computer science curriculum includes so many topics, adding a new course as a required part of the curriculum without increasing the number of hours to graduation is difficult. Integration of heterogeneous computing requires a module-driven approach in which coverage of the topics is broken down into smaller units and dispersed throughout the curriculum. The module-driven approach has been successfully implemented in introducing parallel and distributed computing concepts. In this paper, we present a set of four teaching modules that introduce fundamental concepts in heterogeneous computing in lower-division computer science courses. The goal of these modules is not to teach students how to program heterogeneous systems but rather to expose them to this emerging trend and prepare them for material in future classes. Although concepts are covered at a high level, the modules emphasize active learning and include lab assignments that provide students with hands-on experience. We also present initial evaluation results for two of these modules based on their use in undergraduate courses at Texas State University. The results are quite encouraging both in terms of learning outcomes and student engagement and interest. [ABSTRACT FROM AUTHOR]

• A series of short, self-contained learning modules on bigdata and cloud computing were developed and dispersed over several core CS courses. • Modules are designed following established learning theories that adequately characterizes the embraced competency-based model. • Modules provide hands-on experiences using cloud analytics engines such as Hadoop and Spark on popular cloud platforms. • The GitHub repository of modules is available for broader adoption. • Student performance and survey results show reasonable success in attaining learning outcomes and enhanced interests. Big data and cloud computing collectively offer a paradigm shift in the way businesses are now acquiring, using, and managing information technology. This creates the need for every CS student to be equipped with foundational knowledge in this collective paradigm and possess some hands-on experience in deploying and managing big data applications in the cloud. This study argues that, for substantial coverage of big data and cloud computing concepts and skills, the relevant topics need to be integrated into multiple core courses across the CS curriculum rather than creating additional courses and performing a major overhaul of the curriculum. Our approach to including these topics is to develop autonomous competency-based learning modules for specific core courses in which their coverage might find an appropriate context. In this paper, four such modules are discussed, and our classroom experiences during these interventions are documented. Student performance data and survey results show reasonable success in attaining student learning outcomes, enhanced engagement, and interests. [ABSTRACT FROM AUTHOR]

• An intelligent taxi dispatch system for big cities validated by real-world dataset. • Taxi demand and destination prediction based on historical data. • Realtime taxi assignment and reallocation strategy to optimize multiple goals. • Performance comparison with several popular prediction and optimization strategies. In this paper we describe an intelligent taxi dispatch system that has the goal of reducing the waiting time of the passengers and the idle driving distance of the taxis. The system relies on two separate models that predict the probability distributions of the taxi demand and destinations respectively. The models are learned from historical data and use a combination of long short term memory cells and mixture density networks. Using these predictors, taxi dispatch is formulated as a mixed integer programming problem. We validate the performance of the predictors and the overall system on a real world dataset of taxi trips in New York City. [ABSTRACT FROM AUTHOR]

Recently, FPGA has been utilized to accelerate the Random Forest prediction process to meet the speed requirements of real-time tasks. However, the existing accelerators impose restrictions on the parameters of the accelerated model. The accelerators have to be reconfigured to adapt to a model whose parameters exceed the predefined restrictions. When these accelerators are applied in the scenarios where the model updates or switches frequently, non-trivial time overhead and maintenance costs may be introduced. To solve the above problem, a flexible accelerator RF-RISA, Random Forest Reduced Instruction Set Accelerator, is presented in this paper. Compared with the existing accelerators, RF-RISA eliminates all the restrictions by decoupling the model parameters from its hardware implementation. Specifically, RF-RISA encodes the information of the model into a group of instructions, then the instructions are stored in the memory rather than are hardcoded in the hardware. Meanwhile, a mapping scheme is proposed to map the instructions into the memory dynamically. Finally, a new hardware architecture is designed to support the pipelined computing. The theoretical analysis and experimental results show that the proposed RF-RISA can accelerate a wide range of RF models without reconfiguration. At the same time, it can achieve the same throughput as the state-of-the-art. • A flexible Random Forest prediction accelerator for multiple applications. • A Random Forest representation method based on an instruction set. • The memory of FPGA are allocated to store the nodes on demand. • A new pipelined hardware architecture for accelerating Decision Tree. [ABSTRACT FROM AUTHOR]

• A new multi-attribute authority attribute-based signature scheme (MA-ABS) with constant-size. • An anonymous handover authentication protocol using MA-ABS and consortium blockchain. • Using tamper-resistant blockchain to save user's pseudonym tags and public keys of AP nodes. • Providing fine-grained access control and efficient handover for mobile users. Given the ubiquitous nature of wireless networks in today's society, protecting users' information and identity during handover authentication is paramount. Mobile network operators hope to implement a more flexible and fine-grained authentication to provide better and safer services. In this paper, we propose a new multi-attribute authority attribute-based signature (MA-ABS) scheme that has a constant-size signature. More specifically, we propose an anonymous handover authentication protocol that uses MA-ABS and consortium blockchain. This new protocol not only has fine-grained access control, but it protects the user's privacy and ensures an efficient and private handover. [ABSTRACT FROM AUTHOR]

• The placement of data and the scheduling of request are studied in edge caching. • Network unreliability and limited storage and bandwidth resources are considered. • Two algorithms with different computation complexity and cache efficiency are developed. • The experiments are conducted to evaluate the performance of proposed caching strategies. Edge caching is a prevailing media delivery technology where data is hosted at the edge nodes with computing and storage capability in close proximity to users, in order to expand the backhaul network capacity and enhance users' quality of experience (QoE). The existing work in this area often neglects the fact that large-scale distributed cache networks are not particularly reliable and many edge nodes are prone to failure. In this paper we investigate and develop a novel, cooperative caching mechanism for content placement and request routing. We aim to minimize the content access delay and achieve the optimization in polynomial time, taking into account failures in an unreliable network environment with limited edge storage and bandwidth. We introduce two optimization algorithms: 1) a primal-dual algorithm that is based on the Lagrangian dual decomposition and subgradient method, and 2) a greedy-based approximation algorithm with a proven approximation ratio. Numerical results show that the proposed algorithms outperform other comparative approaches in synthetic and real network environments, and the approximation algorithm is particularly suitable for networking scenarios with sparse node connectivity and resources in short supply. [ABSTRACT FROM AUTHOR]

• A new mesh-based method for designing unstructured mesh particle-in-cell simulations. • Implementation details of a library, PUMIPic, using the mesh-based approach on GPUs. • Analysis of mesh-based scaling on a pseudo physics simulation built with PUMIPic. Unstructured mesh particle-in-cell, PIC, simulations executing on the current and next generation of massively parallel systems require new methods for both the mesh and particles to achieve performance and scalability on GPUs. The traditional approach to implementing PIC simulations defines data structures and algorithms in terms of particles with a full copy of the unstructured mesh on every process. To effectively scale the unstructured mesh and particles, mesh-based PIC uses the unstructured mesh as the predominant data structure with the particles stored in terms of the mesh entities. This paper details the PUMIPic library, a framework for developing efficient and performance-portable mesh-based PIC simulations on GPU systems. A pseudo physics simulation based on a five-dimensional gyro-kinetic code for modeling plasma physics is used to examine the performance of PUMIPic. Scaling studies of the unstructured mesh partition and number of particles are performed up to 4096 nodes of the Summit system at Oak Ridge National Laboratory. The studies show that mesh-based PIC can utilize a partitioned mesh and maintain scaling up to system limitations. [ABSTRACT FROM AUTHOR]

• Presents the systematic literature review on fog computing. • Aims to classify and investigate the recently published work statistically in fog computing. • Proposes a taxonomy for fog computing frameworks. • Compares the existing studies based on the common characteristics and properties. • Highlights current research challenges, future directions and emerging trends. There has been rapid development in the number of Internet of Things (IoT) connected nodes and devices in our daily life in recent times. With this increase in the number of devices, fog computing has become a well-established paradigm to optimize various key Quality of Service (QoS) requirements such as latency, bandwidth limitation, response time, scalability, privacy and security. In this paper, we present a systematic literature review of fog computing. This review article aims to classify recently published studies and investigate the current status in the area of fog computing. In this work, we have discussed the important characteristics of fog computing frameworks and identified various issues related to its architectural design, QoS metrics, implementation details, applications and communication modes. We have proposed taxonomy for fog computing frameworks based on the existing literature and compared the different research work based on taxonomy. Finally, various open research challenges and promising future directions are highlighted for further research in the area of fog computing. [ABSTRACT FROM AUTHOR]

• The Sigmoid algorithm applies the well-known sigmoid function to load balancing. • The algorithm uses all the resources of a system to their fullest requiring no effort. • It adapts to different hardware configurations and application behaviours. • Sigmoid successfully scales to adapt to the systems of the future. A challenge that heterogeneous system programmers face is leveraging the performance of all the devices that integrate the system. This paper presents Sigmoid, a new load balancing algorithm that efficiently co-executes a single OpenCL data-parallel kernel on all the devices of heterogeneous systems. Sigmoid splits the workload proportionally to the capabilities of the devices, drastically reducing response time and energy consumption. It is designed around several features; it is dynamic, adaptive, guided and effortless, as it does not require the user to give any parameter, adapting to the behaviour of each kernel at runtime. To evaluate Sigmoid's performance, it has been implemented in Maat, a system abstraction library. Experimental results with different kernel types show that Sigmoid exhibits excellent performance, reaching a utilization of 90%, together with energy savings up to 20%, always reducing programming effort compared to OpenCL, and facilitating the portability to other heterogeneous machines. [ABSTRACT FROM AUTHOR]

Mobile devices (MDs) and applications are receiving extensive popularity and attracting significant attention. Mobile applications, especially for artificial intelligence (AI) applications, require powerful computation-intensive resources. Hence, running all the AI applications on a single MD introduces high energy consumption and application delay, as it has limited battery capacity and computation resources. Fortunately, the emerging edge-cloud computing (ECC) architecture pushes the computation resource to both the network edge and remote cloud to cope with challenging AI applications. Although the advantage of ECC greatly benefits various mobile applications, data security remains an important open issue in this scenario, which has not been well studied. This paper focuses on the profit maximization (PM) problem for security-aware task offloading in an ECC environment, i.e., considering the tasks from MDs with different service demands, edge nodes should decide them to be processed on the edge node or the remote cloud with a security guarantee. Specifically, we first construct the security model to measure the time overhead for each task under various scenarios. We then formulate the PM problem by jointly considering the security demand and deadline constraints of tasks. Finally, we propose a genetic algorithm-based PM (GA-PM) algorithm, the coding strategy of which considers the task execution location and execution order. Moreover, the crossover and mutation operations are implemented based on the coding strategy. Extensive simulation experiments with various parameters varying demonstrate that our GA-PM can achieve better performance than all the comparison algorithms. • The security model is built to measure the execution time of tasks under different parameters. • A genetic algorithm (GA)-based PM algorithm is proposed to implement task offloading and obtain optimal profit. • A coding strategy is devised by considering the tasks execution location and execution order. • Extensive simulation results demonstrate that GA-PM algorithm achieves the optimal profit. [ABSTRACT FROM AUTHOR]

Blockchain is a relative recent research and technological trend, with applications in diverse domains including those associated with a nation's critical infrastructure sectors (e.g., chemical, commercial facilities, communications, critical manufacturing, dams, defense industrial base, emergency services, and energy). The interest in blockchain is also partly evidenced by the number of submissions we received in this special issue. Of the 54 submissions received, 18 papers were accepted after several rounds of reviews by subject matter experts (i.e., acceptance rate of ∼ 33.3%). This special issue presents the research advances and describes existing and emerging challenges outlined in these 18 accepted papers, authored by researchers from institutions in Australia, Canada, China, Denmark, Ireland, New Zealand, Spain, United Kingdom, and United States. These accepted papers also reinforce the importance of collaboration across institutions and countries. [ABSTRACT FROM AUTHOR]

High Performance Computing (HPC) is a highly demanded discipline in companies and institutions. However, as students and also afterwards as professors, we observed a lack of HPC related content in the engineering degrees at our university, including Computer Science. Thus, we designed and offered the engineering students a non-mandatory course entitled "Build your own cluster employing Raspberry Pi" to provide the students with HPC skills. With this course, we covered the basics of supercomputing (hardware, networking, software tools, performance evaluation, cluster management, etc.). This was possible thanks to leveraging the flexibility and versatility of Raspberry Pi devices, and the students' motivation that arose from the hands-on experience. Moreover, the course included a "Teaching on demand" component to let the attendees choose a field to explore, based on their own interests. In this paper, we offer all the details to let anyone fully reproduce the course. Besides, we analyze and evaluate the methodology that let us fulfill our objectives: increase the students' HPC skills and knowledge in such a way that they feel capable of utilizing it in their mid-term professional career. • On-demand teaching helps in the adaption to the students' learning pace. • Compacting learning hours increases the contents to be covered in a hands-on course. • Raspberry Pi devices help to raise students' motivation. • Human resources are essential for successful on-demand teaching. • Get started in HPC can be done with reasonable hardware costs. [ABSTRACT FROM AUTHOR]

• We propose a novel certificateless public auditing scheme for data shared in a group. • The proposed scheme supports shared data dynamics and group user revocation. • We prove that our scheme protects the data privacy against verifier during the integrity checking process. With the increasing popularity of data sharing among users of a group in clouds, shared data auditing has become an important issue in the cloud auditing field. To address this issue, many shared data auditing schemes have been proposed in the literature based on either public key infrastructure (PKI) or identity-based cryptography (IBC). However, these schemes suffer from issues of complex certificate management or key escrow problem. To address these problems, recently, a certificateless shared auditing scheme was put forward. However, it cannot support data dynamics and does not protect data privacy against a verifier, i.e., the verifier can derive data content when verifying the data integrity, which affects the scheme's security. This paper proposes certificateless privacy preserving public auditing scheme for dynamic shared data with group user revocation in cloud storage (CLPPPA). CLPPPA protects the privacy of data from the verifier by leveraging a random masking technique. Further, CLPPPA also supports shared data dynamics and group user revocation. We formally prove the security of CLPPPA under computational Diffie-Hellman (CDH) and discrete logarithm (DL) assumptions in the Random Oracle Model (ROM). The performance of CLPPPA is evaluated by theoretical analysis, experimental results, and compared with the state-of-the-art ones. The results demonstrate that CLPPPA achieves desirable efficiency. [ABSTRACT FROM AUTHOR]

• Labs from different courses addressing the implementation of a ray tracer. • Detailed descriptions of every lab, including code snippets and lab interactions. • Suitability study of different computing boards to run the proposed experience. • Discussion on technical results that students should reason about. • Qualitative assessment of the proposed labs with pre and post surveys. In the curriculum of a Computer Engineering program, concepts like parallelism, concurrency, consistency, or atomicity are usually addressed in separate courses due to their thoroughness and extension. Isolating such concepts in courses helps students not only to focus on specific aspects, but also to experience the reality of working with modern computer systems, where those concepts are often detached in different abstraction levels. However, due to such an isolation, it exists a risk of inducing to the students an absence of interactions between these concepts, and, by extension, between the different abstraction levels of a system. This paper proposes a learning experience showcasing the interactions between abstraction levels addressed in laboratory sessions of different courses. The driving example is a parallel ray tracer. In the different courses, students implement and assemble components of this application from the algorithmic level of the tracer to the assembly instructions required to guarantee atomicity. Each lab focuses on a single abstraction level, but shows students the interactions with the rest of the levels. Technical results and student learning outcomes through the analysis of surveys validate the proposed experience and confirm the students learning improvement with a more integrated view of the system. [ABSTRACT FROM AUTHOR]

HDFS faces several issues when it comes to handling a large number of small files. These issues are well addressed by archive systems, which combine small files into larger ones. They use index files to hold relevant information for retrieving a small file content from the big archive file. However, existing archive-based solutions require significant overheads when retrieving a file content since additional processing and I/Os are needed to acquire the retrieval information before accessing the actual file content, therefore, deteriorating the access efficiency. This paper presents a new archive file named Hadoop Perfect File (HPF). HPF minimizes access overheads by directly accessing metadata from the part of the index file containing the information. It consequently reduces the additional processing and I/Os needed and improves the access efficiency from archive files. Our index system uses two hash functions. Metadata records are distributed across index files using a dynamic hash function. We further build an order-preserving perfect hash function that memorizes the position of a small file's metadata record within the index file. • Direct metadata access using perfect hashing. • Archive base solution to HDFS small files problems. • Small files access performance optimization using hashing techniques. • Dynamic index files. [ABSTRACT FROM AUTHOR]

• A framework for cross-domain secure data sharing in the Industrial Internet of Things. • A system to manage false reporting and misbehaving using a penalty mechanism. • A framework for enhancing data integrity through multi-layer signatures. The Industrial Internet of Things (IIoT) enhances smart manufacturing process that escalates productivity through revolutionary techniques. The manufacturing process is sophisticated and complex because of various IoT domains (e.g. industries). A final product is an outcome of the efforts of several departments from different industries. However, this raises the cross-domain communication's privacy and security issues. Cross-domain data sharing for product manufacturing is a challenging research direction. This paper proposes a centralized cloud-based cross-domain data sharing platform using multiple security gateways. The security gateways use the blockchain to store the information into the centralized cloud. Once the application reported a malicious activity, the centralized cloud verifies the concern from the blockchain. Further, an action is taken against the party that performs malicious activity in the security gateways. The algorithms are designed for authentication and transaction of data. The proposed framework is able the secure data movement among different domains globally. The experiment result demonstrates that the proposed security and privacy framework helps to maintain trust among the industries that collaborate on manufacturing across the domains. [ABSTRACT FROM AUTHOR]

• Enumeration of design guidelines for 100+ Gbps flow probe on commodity servers. • NUMA aware pipelined architecture with localized compute and memory operations. • Architecture for flow capture, compute and export for 100 Gbps Internet like traffic. • Validation with experimental results on a multi-core multi-processor platform. • Demonstration of scalable performance for 300 Gbps with additional NUMA nodes. The unrelenting growth of data intensive applications has been raising the bar for performance of high speed networks. To cater for this growth, the core segments of networks today are based on 100 Gbps links. Analyzing the huge volume of traffic over these networks is a challenging yet essential task from the perspectives of network administration, network security and law enforcement. In spite of the availability of adequate network, compute, and memory resources, designing traffic analysis solutions performing at line rate for high speed traffic brings up several challenges. Traffic analysis solutions built on commodity compute platforms bring distinct advantages in terms of cost, adaptability, up-gradation and scalability. Keeping this in view, this paper explores the feasibility of designing high speed traffic analysis solutions that can handle 100s of Gbps on commodity compute platforms. It begins this process by analyzing the design issues in line rate handling of traffic on commodity servers with 100 GbE NIC and by bringing out an optimized and scalable packet processing pipeline. Leveraging this processing pipeline, NAPA-FP, a NUMA aware flow probe architecture, has been designed. With an implementation of this architecture on a commodity server, we show that line rate processing of Internet-like traffic from a 100 GbE interface can be achieved with a single NUMA node, by using a suitably configured packet processing path. We also show that its performance scales linearly to multiple 100 Gbps with additional NUMA nodes and NICs. In particular, the implementation on a 4-socket commodity server with 3 × 100 GbE NICs is able to process 3 × 100 Gbps Internet-like traffic at line rate using 3 NUMA nodes. The optimizations with respect to resource allocation, sharing and processing pipeline are reported with corroborating experimental results. [ABSTRACT FROM AUTHOR]

Training on Grid technologies has traditionally used existing Grid infrastructures to implement the hands-on education activities. However, these infrastructures are insufficient to develop all training skills as they can only be employed for the development of Grid applications, and they are limited for learning the management and configuration of Grid resources. The paper presents a set of educational activities grouped on a Project Based Learning (PBL) framework for training on Grid technologies. A Cloud-based tool has been implemented to provide Grid infrastructures as a Service on the cloud, with enhanced scalability and administration capabilities. The PBL has achieved a high impact in the teaching-learning process, addressing the training in all the necessary skills and efficiently providing Grid infrastructure resources on public clouds at a moderate cost. Finally, we evaluated the students' opinion on the activities achieving a very satisfactory result and a reasonable balance on the complexity of the PBL stages. • Cloud Computing improves teaching activities on Grid Computing. • Grid as a Service provides Virtual Grid Infrastructures to improve PBL activities. • Grid as a Service allows addressing the Grid training in all related skills. • Grid as a Service provides Grid infrastructures without scalability and administration limits. • Cloud computing provides Grid infrastructure resources on public clouds at a moderate cost. [ABSTRACT FROM AUTHOR]

• An approach for safe and efficient systems of concurrent communicating agents. • We define a DaHL system as a fused set of open time-dependent colored Petri nets. • We define a reachability graph for DaHL systems. • We model and analyze a scenario of autonomous vehicles in an enterprise environment. This paper provides a true-concurrency approach for the specification and verification of systems of concurrent communicating agents with durable actions. We present high-level Petri nets with durable actions (DaHL) to cope with various details in such complex systems. We define a DaHL module as an open variant of time-dependent colored Petri nets. A DaHL system is a fused set of modules for systems consisting of concurrent agents which can interact with each other. We also introduce hybrid-based reachability graph that covers the entire state space of DaHL systems with a true-concurrency semantics. We show that such reachability graph allows us to check important properties such as deadlock-freeness, liveness, home space, and reversibility, and also to predict timing properties prior to real implementation. A case study is used to model and analyze a simple scenario where autonomous vehicles are able to transport containers freely in an enterprise environment. [ABSTRACT FROM AUTHOR]