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Abstract: This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms. [Copyright &y& Elsevier]

Abstract: Integration of hundreds of processors on a chip will become practical thanks to ultra-deep submicron VLSI technology. As wiring delay becomes a bottleneck for a scalable design, on-chip interconnects turn into the critical issues for system performance and reliability. To mitigate long wiring delay impact, wireless on-chip communication infrastructures featuring hybrid mechanisms exploiting both wired and wireless communications have been proposed. By shortening long distance transmission latency and lowering wired network overhead, overall system transfer latency and energy dissipation are improved accordingly. However, unbalanced traffic management reduces the benefit of high speed wireless links so that wired networks also degrade accordingly. To extract the best performance for these hybrid networks, an intelligent congestion-aware router design is needed to balance traffic load and eliminate congestion delay. A sophisticated routing scheme accommodating more throughput and featuring light weight congestion-aware mechanism which uses the number of blocking buffers as a guideline to avoid serious congestion was designed and evaluated. Modified 7-port routers achieve better performance and the proposed routing algorithm successfully eliminates congestion scenarios and efficiently balances traffic loads. This is the first work to exchange congestion information locally and globally to improve network utilization and transmission quality. The experimental results showed significant improvement in transfer latency, network throughput and power efficiency with moderate hardware cost overhead. [Copyright &y& Elsevier]

Silent Data Corruptions (SDCs), those errors that escape detection methods, are critical for system designers because they may result in systems failures. In order to catch SDCs, mechanisms should focus on the behavioural aspects of errors in addition to their physical location or error patterns. Therefore, protection codes like parity, hamming, and the Reed-Solomon code, which heavily depend on the physical location of data bits, are not enough in processors for detection of computing errors. Using characterizing data behaviour during program executions, we have observed value locality in results of destination register for each instruction binary code (instruction opcode and operand codes). This locality exists not only in the results of each instruction, but also in the results of instructions at different memory locations having the same binary code. As a result, an architecture called Instruction Result History Table (IRHT) is presented, which is indexed by the instruction binary code. In the IRHT, a history of values produced by the same instruction binary codes are stored in and utilized during each instruction execution cycle. Any mismatch between the stored values in the IRHT and those generated by current execution, indicates an SDC syndrome. To confirm having SDCs with a high level of confidence, a second execution of the current instruction is issued. A duplication of the execution confirms whether SDC occurred. In the case of SDCs, a third instruction execution with the help of a majority voting frees the system of SDC. Several extensive simulations showed that, up to 83.54% of SDCs are detectable with the help of this locality. Moreover, with the small hardware, IRHT, i.e., 16 kB size, 80.66% of SDCs can be detected on average. Note that the presented method can detect those errors that escape conventional detection mechanisms. So, it can be utilized in conjunction with other conventional methods. [ABSTRACT FROM AUTHOR]

Nanotechnologies, notably quantum-dot cellular automata, have achieved world-wide attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, energy consumption and latency of circuits, is considered as a potential alternative for the CMOS technology. Considering the manufacturing aspects, in this paper, a method is proposed for designing efficient quantum-dot cellular automata circuits. We inspect an alternative approach for streamlined design of quantum-dot cellular automata circuits such that the required external fixed inputs are substantially reduced. In order to demonstrate the efficiency of the proposed method, the widely used multiplexer, XOR and party generator circuits are considered as case studies. All of the proposed circuits are simulated and verified using QCADesigner which is a valid and popular simulation tool. Comparisons indicate that the proposed method considerably reduces the number of external fixed inputs which simplifies the overall circuit implementation and fabrication. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. In this study a low complexity and energy-efficient QCA T flip–flip as well as high-performance single-layer synchronous counters are proposed. By cascading the proposed T flip-flop and a suitable level converter, a QCA-compatible structure for falling edge triggered T flip-flop is achieved. This circuit functions as the chief element for constructing synchronous counters. QCADesigner and QCAPro tools are used for evaluating the functionality and calculating dissipated energy of the circuits, respectively. Results indicate the superiority of the proposed circuits in terms of complexity, latency and energy consumption as compared to their state-of-the-art counterparts. The proposed T flip-flop demonstrates 18% leakage energy improvement besides the considerable value of 56% switching energy improvement in 0.5Ek tunneling energy level as compared to the best ones. It is worth mentioning that 41%, 44% and 45% optimizations in the number of cells in addition to 15%, 25% and 33% optimizations in the area are achieved for the proposed mod 4, mod 8 and mod 16 counters, respectively, in comparison with the best previous results. [ABSTRACT FROM AUTHOR]