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In the Internet of Things era, with millions of devices performing financial and commercial operations, decimal arithmetic has become very popular in the computation of many business and commercial applications, in order to maintain decimal rounding and precision. This paper proposes the design and implementation of a new algorithm for decimal multiplication oriented to area reduction. This algorithm is especially suitable for field programmable gate arrays (FPGA) and has thus been implemented on this kind of devices. Results show that the proposed BCD multiplication leads to a significant area reduction without decreasing system performance. [ABSTRACT FROM AUTHOR]

Elliptic curve point multiplication is considered to be the most significant operation in all elliptic curve cryptography systems, as it forms the basis of the elliptic curve discrete logarithm problem. Designs for elliptic curve cryptography point multiplication are area demanding and time consuming. Thus, the efficient realization of point multiplication is of fundamental importance for the performance of an elliptic curve system. In this paper, a hardware architecture of an elliptic curve point multiplier is proposed that exploits the intrinsic parallelism of the residue number system (RNS), in order to speed up the elliptic curve point calculations and minimize the area complexity of the elliptic curve point multiplier. The architecture proves to be the fastest among all known design approaches, while complexity is less than half of that of previous efforts. This architecture also supports the required input (binary-to-RNS) and output (RNS-to-binary) conversions. Through a graph-oriented approach, the area of the elliptic curve point multiplier is minimized, by optimizing the point addition and doubling algorithms. Also, through this approach, the number of execution steps for point addition is matched to the number of execution steps for point doubling. Additionally, the impact of various RNS bases, in terms of number of moduli and their bit lengths, on the area and speed of the proposed implementation is analyzed, in an effort to define the potential for using RNS in elliptic curve cryptography. [ABSTRACT FROM AUTHOR]

A graph-based technique is introduced for the design of a class of residue arithmetic multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-rn multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases. [ABSTRACT FROM AUTHOR]

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed. [ABSTRACT FROM AUTHOR]