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This is a panel paper that discusses the use of Artificial Intelligence (AI) technologies to address production and supply chain level problems in semiconductor manufacturing. We have gathered a group of expert semiconductor researchers and practitioners from around the world who have developed AI solutions for various semiconductor problems. This paper aims to provide their answers to an initial set of questions and provide an overview of the AI developments and empirical studies to make suggestions for future directions in this arena. [ABSTRACT FROM AUTHOR]

In manufacturing industries, it is of fundamental importance to detect anomalies in production in order to meet the required quality goals and to limit the number of defective products that are accidentally delivered to the customers. Nevertheless, monitoring systems currently employed in production are typically very simple and rely on a set of univariate control charts that fail to capture the multivariate and complex nature of real-world industrial systems. In such context, Machine Learning (ML)-based approaches for Anomaly Detection (AD) have proven to be extremely effective in increasing anomalies detectability and, in general, in enhancing monitoring procedures. However, industrial data are typically very complex and not suitable to be fed directly to classical ML-based AD tools making feature extraction procedures a necessary step that unfortunately may lead to information loss and low scalability. Deep Learning, has proven very effective at learning useful representations of complex data in an automatic way. In this paper, we propose an AD pipeline that makes use of convolutional autoencoders to extract useful features from two-dimensional, non-image, data. We test our approach on real world Optical Emission Spectroscopy data that are typical of semiconductor manufacturing and we achieve improved performance over classical monitoring methods. Note to Practitioners—Advanced monitoring is one of the most important task in the context of Industry 4.0. Some of the main issues in developing Machine Learning-based solutions in industrial environment are: (i) the lack of reliable tagged data; (ii) the complexity of data structures present in real-world scenarios. In this paper we investigate unsupervised anomaly detection for 2-dimensional data in manufacturing environment: we provide an approach that exploit Deep Learning-based architecture for handling the data at hand. We show the effectiveness of the proposed approach in a real world case study related to optical emission spectroscopy data in semiconductor manufacturing process providing satisfactory classification accuracy. [ABSTRACT FROM AUTHOR]

Semiconductor fabrication involves hundreds of process steps through various manufacturing tools. These processing steps are composed of many manufacturing and inspection steps. Inspection is an important step in the fabrication process to determine whether a process is in or out of control. Abrupt manufacturing or inspection tool excursion can lead to a serious low yield problem. Although commonality analysis is a proven tool for detecting abrupt tool excursion, it has gained only limited success in detecting manufacturing tool excursion outside of inspection tools. Compared with manufacturing tools, only a small number of lots or wafers pass through inspection tools. Therefore, it is difficult to construct a sufficient lot history log for inspection commonality analysis in contrast to that of manufacturing tools. Furthermore, inspection may stress a wafer during its own processing, therefore, the target wafer is changed sequentially or randomly. Accordingly, a lot history is apt to include missing traces, which hinders finding inspection tool excursion effectively. In this paper, we propose a comparative analysis framework for commonality analysis algorithms. Performance measures are suggested. To compare the performance of the algorithms effectively, we use a synthetically generated dataset in a simulation experiment. In addition, we apply the algorithms to a real problem that occurred in the fabrication process. Our proposed algorithm demonstrates superiority over the other commonality analysis algorithms in the experiments. [ABSTRACT FROM AUTHOR]

Equipment at the end of functional life poses several challenges for manufacturing operations and long-term asset sustainability. This is even critical for semiconductor manufacturing where equipment upgrades are capital intensive with a longer return horizon. This demands an objective and quantifiable approach to manage and monitor the end-of-life health of the manufacturing systems. The paper presents a practical three-level approach that brings together engineering, operational, and supply chain factors under a single indicator. A visualization heatmap correlates equipment health to manufacturing impact for engineering and commercial decision-making. The approach is simple yet proven to be effective in fab environments. The proposed analysis applies in formulating system priorities, upgrade strategies, and capital expenditures. Brief guidance on health improvement strategies, application to new fab, and cost-based evaluation are presented for practical use. [ABSTRACT FROM AUTHOR]

The concepts of Industry 4.1 for achieving Zero-Defect (ZD) manufacturing were disclosed in IEEE Robotics and Automation Letters in January 2016. ZD of all the deliverables can be achieved by discarding the defective products via a real-time and online total inspection technology, such as Automatic Virtual Metrology (AVM). Further, the Key-variable Search Algorithm (KSA) of the Intelligent Yield Management (IYM) system developed by our research team can be utilized to find out the root causes of the defects for continuous improvement on those defective products. As such, nearly ZD of all products may be achieved. However, in a multistage manufacturing process (MMP) environment, a workpiece may randomly pass through one of the manufacturing devices with the same function in each stage. Different devices of the same type perform differently in each stage, where the performances will be accumulated through the designated manufacturing process and affect the final yield. KSA can only identify the influence of univariate variables (i.e., single devices) on the yield, yet it cannot detect the manufacturing paths that have significant influence on the yield. In order to cope with this deficiency such that the golden path with a better yield amongst all the MMP paths can be found, this research proposes the Golden Path Search Algorithm (GPSA), which can plan golden paths with high yield under the condition of the number of variables being much larger than that of samples. As a result, it makes the improvement of manufacturing yield be more comprehensive. Note to Practitioners—Traditional scheduling only considers the capacity of the manufacturing devices for allocation; while, the impact on the yield is rarely considered. In fact, in a production process, the production deviations will be gradually accumulated and affect the product quality along with the processing influence of each device. Therefore, the purpose of this paper is to propose the GPSA scheme to quickly search for high-yield manufacturing paths before the production. Manufacturers can then configure production devices based on these paths. According to the experimental results of real manufacturers’ data, GPSA can not only quickly nail down the high-yield paths from a large amount of historical data, but also alert the users to avoid paths that are prone to defective rates for their reference. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. [ABSTRACT FROM AUTHOR]

Semiconductors are essential components in many electronic devices. Because wafers are produced quickly and in large quantities, defects occur that adversely affect semiconductor properties. This makes it necessary to install powerful and robust inspection systems which use artificial intelligence techniques in the early stages of the manufacturing chain in order to detect and classify those defects. This paper proposes a method for defect detection and classification on images of semiconductor wafer materials obtained by means of a scanning electron microscope based in the following stages: (i) use of computer vision techniques to isolate the defect from the background; (ii) use of several descriptors based on shape, size, texture, histogram, and key-points to create a feature vector for the characterization of the defect; (iii) application of an exhaustive search as a feature selection method to determine the optimal subset of feature descriptors; and (iv) evaluation of the feature descriptors by using a support vector machine classifier providing the optimal set with highest F1-score metrics. Finally, the effectiveness of the proposed approach is compared with five popular feature selection methods, reporting better classification results than the latter. [ABSTRACT FROM AUTHOR]

Metrology, which plays an important role in ensuring production quality in modern manufacturing industries, incurs substantial costs both in terms of the infrastructure required and the time needed to perform measurements. In particular, in the semiconductor manufacturing industry, measuring fundamental quantities on different sites of a wafer surface is associated with increased production time. To increase metrology efficiency, a typical strategy is to limit the number of sites measured and to exploit statistical models (soft sensing) to reconstruct the wafer profile. Moreover, for quality reasons, spatial dynamic sampling strategies may be employed to ensure that all regions of a wafer surface are checked periodically during production. In this paper, we propose a new sampling strategy, called induced start dynamic sampling (ISDS), which adapts greedy feature selection algorithms to the spatial dynamic sampling problem, such that the number of measured sites at each process run is minimized while achieving good wafer profile reconstruction accuracy and process visibility. The superiority of the proposed strategy with respect to the state of the art is demonstrated using both simulated data and an industrial chemical vapor deposition case study. Note to Practitioners—In this paper, we tackle a practical metrology problem encountered in semiconductor manufacturing, namely, the design of a dynamic wafer measurement plan to monitor the accuracy of a process across the whole wafer surface. The measurement plan is called “dynamic,” since the measurement locations, which are drawn from a candidate set that provides coverage of the whole wafer, change at each process iteration. Our methodology addresses the challenge of finding an optimized tradeoff between the number of measurements performed on each wafer and the reconstruction accuracy that can be achieved for the unmeasured areas on the wafer while, at the same time, for quality assurance purposes, ensuring that all locations on a wafer are visited in a finite number of process runs. The major benefit of the methodology is that it can significantly reduce the number of sites that need to be measured on each wafer enabling greater throughput on metrology tools without sacrificing process monitoring and anomaly detection capability. [ABSTRACT FROM AUTHOR]

Searching for and comparing similar wafer maps can provide crucial information for root cause analysis in the manufacturing process of integrated circuits. Owing to the high dimensionality and complexity of defect patterns, comparison of similar maps in their entirety is inefficient. This paper proposes an automated similarity ranking system with a novel feature set as a reduced representation of wafer maps. To detect systematic failure patterns across wafer maps, we use nonparametric Bayesian clustering based on the Dirichlet process Gaussian mixture model, and hierarchical clustering based on the symmetric Kullback–Leibler divergence. The proposed features are efficient because they require minimal computation and storage; furthermore, they allow for highly discriminative rankings of similar failure patterns. Thus they are suitable for large-scale analysis of wafer maps. The proposed method is experimentally verified using a real wafer map dataset from a semiconductor manufacturing company, and a subset of WM-811K. [ABSTRACT FROM AUTHOR]

This paper describes a chamber and recipe-independent fault detection and classification (FDC) indicator using the example of aluminum sputtering tools. We developed this indicator to detect abnormal discharge in an aluminum sputtering chamber when using a legacy FDC system. Abnormal discharge has several modes in the sputtering chamber, with abnormal discharge to a wafer commonly causing pattern defects. The indicator has been improved to detect only this problem, and to minimize the impact of false alarms that cause a loss of equipment productivity. The indicator can be readily extended to new chambers and the control limits are easily set for all recipes. This is because the equation for the indicator is very simple, and both the equation and the control limits are common to all sputtering chambers and recipes. It can therefore significantly reduce the setup work required of engineers, which is one of the biggest challenges in high-mix semiconductor manufacturing. The indicator is easily applied to newly installed tools at start of production and restrains the number of scrap wafers at minimum level. We also describe the mechanism of trace data changes in abnormal discharge modes using equivalent electrical circuits. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing is a complicated flexible job-shop scheduling problem (FJSP) of combinatorial complexity. Because of the adoption of advanced process control and advanced equipment control, the processing time in advanced wafer fabs become uncertain. Existing approaches considering constant processing time may not be appropriate to address the present problem in a real setting. In practice, processing times can be represented as intervals with the most probable completion time somewhere near the middle of the interval. A fuzzy number that is a generalized interval can represent this processing time interval exactly and naturally. This paper developed a hybrid approach integrating a particle swarm optimization algorithm with a Cauchy distribution and genetic operators (HPSO+GA) for solving an FJSP by finding a job sequence that minimizes the makespan with uncertain processing time. In particular, the proposed hybridized HPSO+GA approach employs PSO for creating operation sequences and assigning the time and resources for each operation, and then uses genetic operators to update the particles for improving the solution. To estimate the validity of the proposed approaches, experiments were conducted to compare the proposed approach with conventional approaches. The results show the practical viability of this approach. This paper concludes with discussions of contributions and recommends directions for future research. [ABSTRACT FROM PUBLISHER]

Automated inspection systems play an important role in manufacturing to guarantee higher quality and reduce production costs. In the semiconductor manufacturing industry, assembly and testing processes are getting more complex, resulting in a greater tendency of defects to impact the production process. These defects can cause field failures and can result in customer dissatisfactions and returns. Currently available defect detection and classification systems are customized and hard-wired to the detection of particular classes of defects and cannot deal with new unknown classes of defects. This issue is aggravated by the very small sample size of available anomalies for learning, by the data imbalance problem, since the number of defective samples is significantly much smaller than the number of normal samples, and by the presence of noise. This paper presents a novel multifeature, sparse-based defect detection and classification approach that uses the stacking concept to enhance the classification accuracy. The stacking-based classifier is augmented with a novel adaptive over/downsampling technique to deal with the data imbalance problem. A new pruning technique is proposed to eliminate bad base learners. Shortage of defective units, similarities within different classes of defects, wide variation within the same defect class, and data imbalance are the basic challenges to deal with. Experimental results on real-world data from Intel show that the proposed approach results in a high classification accuracy as compared with the existing methods.

Note to Practitioners—The basic motivation of this paper is to design an automated cost-effective, adaptive, and intelligent defect detection and classification system that is easy to train using a small-size sample set of defects and that is robust to noise. The system is scalable in terms of the numbers and types of defects and features, which leads to a shorter development cycle. The presented system is immediately applicable to different types of defects. Inputs of the system are grayscale images. These images are processed to perform defects detection, features extraction, and classification. [ABSTRACT FROM PUBLISHER]

Quality inspection in semiconductor manufacturing is of great importance in the modern industries. In the recent years, intelligent data-driven condition monitoring methods have been successfully developed and applied in the industrial applications. However, despite the promising condition monitoring performance, the existing methods generally assume the training and testing data are from the same distribution. In practice, due to variations in manufacturing process, the collected data are usually subject to different distributions in different operating conditions, that significantly deteriorates the performance of the data-driven methods. To address this issue, this paper proposes a deep learning-based domain adaptation method for fault diagnosis in semiconductor manufacturing. The maximum mean discrepancy metric is optimized on the learned high-level data representation in the deep neural network. Experimental results on a real-world semiconductor manufacturing dataset suggest the proposed method offers an effective and generalized data-driven fault diagnosis approach for quality inspection. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, fabrication processes and their materials should be properly co-optimized to achieve required processing results within reasonable development duration and acceptable cost. Unfortunately, it is a very time-consuming procedure, because the number of possible combinations of process/material candidates is very large. Here, we develop a methodology for co-optimization of processes and their materials. We successfully constructed a prediction model for dry-etching of high- ${k}$ materials (R2 = 0.65). Also, it was proven that considering both the materials and processes is needed for accurate prediction of etching rates. By trying only <0.00001% of all possible process/material candidates with this model and Bayesian optimization, we can find new combinations of gasses and their processes for more than 100 times higher etching rates than that with a traditional gas/process condition. Furthermore, we discussed that accurate prediction can be made by using a combination of the Bayesian optimization with LASSO and materials knowledge from related scientific papers. Future work will focus on validating the versatility of our methodology by applying it to other development items. [ABSTRACT FROM AUTHOR]

In this paper, we focus on a defect analysis task that requires engineers to identify the causes of yield reduction from defect classification results. We organize the analysis work into three phases: defect classification, defect trend monitoring and detailed classification. To support the first and third engineer’s analytical work, we use a convolutional neural network based on the transfer learning method for automatic defect classification. We evaluated our proposed methods on real semiconductor fabrication data sets by performing a defect classification task using a scanning electron microscope image and thoroughly examining its performance. We concluded that the proposed method can classify defect images with high accuracy while lowering labor costs equivalent to one-third the labor required for manual inspection work. [ABSTRACT FROM AUTHOR]

A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. In this paper, we propose a voting ensemble classifier with multi-types features to identify wafer map defect patterns in semiconductor manufacturing. Our research contents can be summarized as follows. First, three distinctive features such as density-, geometry-, and radon-based features were extracted from raw wafer images. Then, we applied four machine learning classifiers, namely logistic regression (LR), random forests (RFs), gradient boosting machine (GBM), and artificial neural network (ANN), and trained them using extracted features of original data set. Then their results were combined with a soft voting ensemble (SVE) technique which assigns higher weights to the classifiers with respect to their prediction accuracy. Consequently, we got performance measures with accuracy, precision, recall, ${F}$ -measure, and AUC score of 95.8616%, 96.9326%, 96.9326%, 96.7124%, and 99.9114%, respectively. These results show that the SVE classifier with proposed multi-types features outperformed regular machine learning-based classifiers for wafer maps defect detection. [ABSTRACT FROM AUTHOR]

At nanometer manufacturing technology nodes, process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign in the traditional worst-case circuit design flow. To combat this pessimism, post-silicon clock tuning buffers can be deployed to balance timing slacks of consecutive combinational paths in individual chips by tuning clock skews after manufacturing. A challenge of this method is that path delays of each chip with timing failures should be measured to gather the information for clock skew configuration. However, current methods for delay measurement rely on path-wise frequency stepping, which requires much time from expensive testers. In this paper, we propose an efficient delay test framework (EffiTest2) to solve the post-silicon testing problem by testing only representative paths with delay alignment using the already-existing tunable buffers in the circuit. Experimental results demonstrate that EffiTest2 can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, a wafer bin map (WBM) represents the results of wafer testing for dies using a binary pass or fail value. For WBMs, defective dies are often clustered into groups of local systematic defects. Determining their specific patterns is important, because different patterns are related to different root causes of failure. Recently, because wafer sizes have increased and the process technology has become more complicated, the probability of observing mixed-type defect patterns, i.e., two or more defect patterns in a single wafer, has increased. In this paper, we propose the use of convolutional neural networks (CNNs) to classify mixed-type defect patterns in WBMs in the framework of an individual classification model for each defect pattern. Through simulated and real data examples, we show that the CNN is robust to random noise and performs effectively, even if there are many random defects in WBMs. [ABSTRACT FROM AUTHOR]

The rise of industry 4.0 and data-intensive manufacturing makes advanced process control (APC) applications more relevant than ever for process/production optimization, related costs reduction, and increased efficiency. One of the most important APC technologies is virtual metrology (VM). VM aims at exploiting information already available in the process/system under exam, to estimate quantities that are costly or impossible to measure. Machine learning (ML) approaches are the foremost choice to design VM solutions. A serious drawback of traditional ML methodologies is that they require a features extraction phase that generally limits the scalability and performance of VM solutions. Particularly, in presence of multi-dimensional data, the feature extraction process is based on heuristic approaches that may capture features with poor predictive power. In this paper, we exploit modern deep learning (DL)-based technologies that are able to automatically extract highly informative features from the data, providing more accurate and scalable VM solutions. In particular, we exploit DL architectures developed in the realm of computer vision to model data that have both spatial and time evolution. The proposed methodology is tested on a real industrial dataset related to etching, one of the most important semiconductor manufacturing processes. The dataset at hand contains optical emission spectroscopy data and it is paradigmatic of the feature extraction problem in VM under examination. [ABSTRACT FROM AUTHOR]

In this paper, a cost-effective, easy-install and fast measurement and analysis method to obtain seismic response of semiconductor manufacturing equipments was developed and its validity was discussed. In the developed method, micro-vibration measurement experiments are first carried out to obtain transfer functions and coherence functions from the floor to arbitrary part of equipment. Using obtained transfer function, seismic response of the arbitrary part of equipment is analyzed with seismic floor response input. In this paper, the developed method was applied to a vertical furnace and a lithography system and their transfer functions were experimentally obtained. It has been confirmed that with additional excitation on the floor near the equipment is effective to improve the accuracy of obtained transfer functions. The validity of developed analysis method was confirmed by the good agreement between the analytical result and the experimental result obtained with a shaking table. The developed method is to be useful to estimate seismic damage of various types of semiconductor manufacturing equipment as well as to take seismic countermeasures. [ABSTRACT FROM AUTHOR]

This paper presents an empirical study, which leads to a theoretical framework that links organizational learning and capital productivity. The approach described in this paper helps fab managers make fundamental strategic decisions concerning capital investment and point of entry by engaging in scenario planning. Three strategic options for semiconductor manufacturing are analyzed in detail—leading-edge manufacturer, fast follower, and slow follower. The study concludes that profitability and capital productivity can be in conflict with each other. Leading-edge manufacturers can make large profits, if they ramp up to volume production in a timely manner, but their return on investment and thus their capital productivity are relatively low. Generally, manufacturers that do not run state-of-the-art processes are less profitable than those that do, but their return on investment and thus their capital productivity is comparatively high. Fast followers, which import part of their manufacturing process and ramp to volume production rapidly but with a delay, neither break even nor recover their investment. [ABSTRACT FROM AUTHOR]

Incorporating virtual metrology (VM) into run-to-run (R2R) control enables the benefits of R2R control to be maintained while avoiding the negative cost and cycle time impacts of actual metrology. Due to the potential for prediction errors from VM models, the prediction as well as the corresponding confidence information on the predictions should be properly considered in VM-enabled R2R control schemes in order to guarantee control performance. This paper proposes the use of Gaussian process regression (GPR) models in VM-enabled R2R control due to their ability to provide this information in an integrated fashion. The mean value of the GPR prediction is treated as the VM value and the variance of the GPR prediction is used as a measure of confidence to adjust the coefficient of an exponentially weighted-moving-average R2R controller. The effectiveness of the proposed GPR VM-enabled R2R control approach is demonstrated using a chemical mechanical polishing process case study. Results show that better control performance is achieved with the proposed methodology than with implementations that do not take prediction reliability into account. [ABSTRACT FROM PUBLISHER]

Many studies on the prediction of manufacturing results using sensor signals have been conducted in the field of fault detection and classification (FDC) for semiconductor manufacturing processes. However, fault diagnosis used to find clues as to root causes remains a challenging area. In particular, process monitoring using neural networks has been employed to only a limited extent because it is a black box model, making the relationships between input data and output results difficult to interpret in actual manufacturing settings, despite its high classification performance. In this paper, we propose a convolutional neural network (CNN) model, named FDC-CNN, in which a receptive field tailored to multivariate sensor signals slides along the time axis, to extract fault features. This approach enables the association of the output of the first convolutional layer with the structural meaning of the raw data, making it possible to locate the variable and time information that represents process faults. In an experiment on a chemical vapor deposition process, the proposed method outperformed other deep learning models. [ABSTRACT FROM PUBLISHER]

Under the trend of globalization, rapid advancement of Information Technology, shorter electronic product life cycles, and the rise of consumer consciousness, there is fiercer market competition in most industries, especially in the semiconductor industry. Effective supply chain management is a critical successful factor for enterprises to survive in such a competitive market since it can help enterprises in reducing cost and improving operational efficiency. For an integrated device manufacturer (IDM) in the semiconductor industry, due to its complex network, strategic alliance among partners as well as supply chain integration are efficient approaches to enhance competitiveness and make more profit. In this paper, we develop an integrated model of supply chain planning for IDMs. The integrated model is developed to help decision makers determine the production quantities and delivery quantities at various locations, the decoupling point of a push–pull supply chain, the inventory buffer at the boundary and the vendor managed inventory scenario. The semiconductor manufacturing characteristics including binning, substitution, and yield are taken into consideration in the formulated model. In addition, the model is developed for a semiconductor supply chain characterized by multiple stages, plants, products, and product grades. [ABSTRACT FROM PUBLISHER]

This paper mainly focuses on the performance of the double exponentially weighted moving average (DEWMA) controller applied to a first-order dynamic input–output model with process drift. Under a general process disturbance, based on Jury test, the necessary and sufficient conditions involving model parameters, the estimated process gain, and weighting factors are established to ensure that the closed-loop system is asymptotically stable. In addition, we explore why we should use the DEWMA controller to adjust the process rather than the single exponentially weighted moving average controller when the process drifts considerably. Later, under the stability condition, the control performance analysis of the closed-loop system is performed in terms of the asymptotical variation and the transient deviation. Then, an optimization model is established to figure out the appropriate weighting factors for reducing the overall variation of the process output during the process of operation. Finally, extensive simulations are carried out to demonstrate the validity of the theoretical analysis in the context of chemical mechanical polishing process. [ABSTRACT FROM PUBLISHER]

Similar to the 300 mm standards, the 450 mm physical interface standards define the multitude of parameters that are essential to factory automation and interoperability. In addition, 450 mm standards drive factory efficiency much farther than the 300 mm standards did. This paper will review the standards architecture and critical parameters defined by the standards with a focus on the efficiency improvements that were incorporated into the 450 mm standards using the learning that the industry has acquired over the last 15 years. We will also outline the steps taken in the industry to test and validate the new 450 mm standards, as well as the preliminary test results. [ABSTRACT FROM AUTHOR]

We consider a scheduling problem of a robotized cluster tool for semiconductor manufacturing, which should control wafer delays within a chamber so as not to exceed a specified limit under time variation. The prior research has proposed a p^+-time event graph, an extension of Petri nets, for modeling the scheduling problem and developed a method of verifying whether a cyclic p^+-time event graph or a cluster tool, which repeats identical work cycles, can satisfy the time constraints under time variation. In this paper, we extend and simplify the schedulability analysis method in the prior research for a noncyclic event graph or a cluster tool which performs start-up and close-down operation for a lot or lot switching, and obtain specialized results. We assume that a robot task sequence or firing sequence of transitions is given. Based on the schedulability analysis, we also propose a way of modifying a not always schedulable noncyclic p^+-time event graph with some qualifications to be always schedulable, that is, we prolong token holding times at some places or equivalently delay firings of some transitions so as to be always feasible. [ABSTRACT FROM PUBLISHER]

Cluster tools each of which consists of processing modules, a transport robot, and loadlocks perform most wafer fabrication processes in semiconductor manufacturing. Recently, the lot size has been decreasing from 25 wafers to even 7–8 wafers due to the larger wafer size and circuit width reduction especially in large-scale integration manufacturing. Hence, the lot switching operation between two consecutive wafer lots occurs frequently. In this paper, we derive closed-form expressions of the makespan of the lot switching period in single-armed and dual-armed cluster tools with the given robot task sequences for the first time. With this research, the completion time of a wafer lot can be easily estimated even though its preceding or next lot is processed together during the lot switching period. Hence, the makespan can be used for integrating operation of overhead hoist transports and cluster tools and assigning wafer lots to cluster tools while minimizing the lot switching period. [ABSTRACT FROM AUTHOR]

This paper presents a scheduling method for semiconductor manufacturing systems through utilizing a case-based reasoning approach that consists of modeling, casebase building, and reasoning steps. Petri nets are employed as a model for representing the behavior of a system and accommodating various types of constraints. Casebase contains the cases, composed of pairs of a state and the decision made at the state, and it is built from the solutions of previously solved problems. Subsequently, a schedule for a new problem with different production requirements, initial setup status, and number of setup change operators is obtained by sequentially retrieving and reusing the cases that are most similar to the states encountered during schedule generation in the reasoning step. Extensive experiments demonstrate the performances of the proposed approach, compared to those of dispatching rule and meta-heuristic methods, and also show the robustness against possible perturbations in terms of production requirements and initial setup status based on real world scale datasets. The proposed method significantly outperformed a meta-heuristic algorithm in terms of computation time while requiring much less sacrifice in a performance metric than the competitive dispatching rules. [ABSTRACT FROM PUBLISHER]

This paper describes the development and the actual utilization of fab-wide fault detection and classification (FDC) for the advanced semiconductor manufacturing using big data. In the fab-wide FDC, the collection of equipment’s big data for the FDC judgment is required; hence, we developed the equipment monitoring system that handles the data in a superior method in high speed and in real time. We succeeded in stopping equipment and lots automatically when the equipment was detected as fault condition. In addition, we developed the environment that enables immediate data collection for analysis by the data aggregation and merging functions, which extracts keys correlating to yield from the equipment’s parameter. Furthermore, we succeeded in development of the high-speed and high-accuracy process control system that implemented virtual metrology and the run-to-run function for the purpose to reduce process variation. [ABSTRACT FROM AUTHOR]

Facility layout problems have drawn much attention over the years, as evidenced by many different versions and formulations in the manufacturing context. This paper is motivated by semiconductor manufacturing, where the floor space is highly expensive (such as in a cleanroom environment) but there is also considerable material handling amongst machines. This is an integrated optimization task that considers both material movement and manufacturing area. Specifically, a new approach combining multiobjective tabu search with linear programming is proposed for an extended double row layout problem, in which the objective is to determine exact locations of machines in both rows to minimize material handling cost and layout area where material flows are asymmetric. First, a formulation of this layout problem is established. Second, an optimization framework is proposed that utilizes multiobjective tabu search and linear programming to determine a set of non-dominated solutions, which includes both sequences and positions of machines. This framework is applied to various manufacturing situations, and compared with an exact approach and a popular multiobjective genetic algorithm optimization algorithm. Experimental results show that the proposed approach is able to obtain sets of Pareto solutions that are far better than those obtained by the alternative approaches. [ABSTRACT FROM AUTHOR]