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This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges. [ABSTRACT FROM AUTHOR]

In current semiconductor manufacturing, limited raw trace data pertaining to defective wafers make fault detection (FD) assignments extremely difficult due to the data imbalance in wafer classification. To mitigate, this paper proposes using a variational autoencoder (VAE) as a data augmentation strategy for resolving data imbalance of temporal raw trace data. A VAE with few defective samples is first trained. By means of extracting the latent variables that characterize the distribution of the defective samples, we make use of the statistical randomness of the latent variables to generate synthesized defective samples via the decoder scheme in the trained VAE. Two data representations and VAE modeling strategies, concatenation of multiple and individual raw trace data as the input of the VAE during the training stage, are investigated. A real-data plasma enhanced chemical vapor deposition (PECVD) process having only few defective samples is used to illustrate the performance enhancement to wafer classification arising from the proposed data augmentation framework. Based on the computational comparisons between noted classification models, the proposed generative VAE model via the individual strategy enables the adaptive boosting (AdaBoost) classifier to achieve perfect performances in every metrics if the 80% and 100% over-sampling ratios are adopted. [ABSTRACT FROM AUTHOR]

To monitor process and identify the deviation as early as possible, data-driven methods have been applied for process monitoring and fault detection in semiconductor manufacturing. Although various fault detection and classification models had been discussed in the literature, however, little research has been devoted to feature selection from trace data that is important for process monitoring of natural variation. Additionally, the high-mix production mode with different recipes leads to process dynamic of wafer-to-wafer (W2W) variation which should also be identified for safeguarding false alarms and serving as a warning indicator. Therefore, this paper proposes a data-driven framework to identify the key features with respect to the W2W variation. In particular, the self-organizing map is used to annotate the grade of wafer variation among the in-line metrology data. Subsequently, the adaptive boosting (AdaBoost) is adopted to examine the effectiveness of every feature and its processing times, respectively. To validate the proposed framework, an empirical study from a semiconductor fabrication plant is conducted. The experimental results demonstrate that the key feature identification is of critical importance to build highly capable models for process monitoring. Through the dimensionality reduction technique, it has been illustrated that a smaller set of the identified key features are able to pinpoint the W2W variation of different wafer grades more clearly than the whole set of process features. Note to Practitioners— Process monitoring has become more difficult with the shrinking linewidth in semiconductor manufacturing. The challenges of analyzing equipment sensor or raw trace data for process monitoring in high-mix manufacturing processes are to incorporate subject-matter expert knowledge for setting control limit meticulously, to detect the subtle changes by analyzing the whole trace data profile, and to identify W2W variation for reducing false alarms. This paper proposes a data-driven framework for process monitoring by adopting data-driven approaches without recourse to domain judgement. Experimental results demonstrate that the proposed data-driven framework can effectively identify the key features via sensor readings and corresponding processing times, respectively. The engineers can make use of the extracted features to perform a predictive monitoring on metrology data for detection of potential process deterioration. [ABSTRACT FROM AUTHOR]

The Czochralski (CZ) process is the core technology for producing semiconductor silicon monocrystalline (SMC), and it is a complex batch process. However, the crystal growth rate and crystal diameter, which are key quality indicators, are difficult to detect directly online, and the offline calculation process lags seriously, which easily causes blind crystal quality control. Therefore, this paper proposes a data-driven and mechanism-based hybrid model for semiconductor SMC quality variables prediction in the CZ process. Firstly, a data-driven model JITL-SAE-ELM based on just-in-time learning (JITL) fine-tuning strategy is proposed. This model is used to solve the nonlinear and time-varying relationship of the energy transfer process in the CZ process that cannot be accurately described by traditional mechanism models. Here, the SAE-ELM model integrates a stacked autoencoder (SAE) and an extreme learning machine (ELM), which are used to deeply capture the nonlinear and time-varying features of process data. Secondly, according to the hydrodynamics and geometric behavior, a crystal pulling dynamic mechanism model based on the crystal growth mechanism is constructed, which avoids the complicated heat transfer link. Further, considering the unmodeled dynamics caused by model parameter uncertainty during the combination of the energy transfer model and crystal pulling dynamic mechanism model, a crystal diameter compensation model SAE-ELM was developed to improve the prediction accuracy of the CZ process hybrid model. Finally, an industrial data experiment based on a CZ monocrystal furnace illustrates the proposed method. [ABSTRACT FROM AUTHOR]

Spectroscopic ellipsometry is a very sensitive optical metrology technique commonly used in semiconductor manufacturing lines to accurately measure the thickness and refractive index of different layers present on specific dedicated metrology targets on the wafers. In parallel, optical defectivity techniques are widely implemented in production lines to inspect a significant amount of dies representative of the full wafer and detect physical and patterning defects. A new approach can then simply emerge which is to apply ellipsometry metrology techniques at a full or die wafer scale. This strategy, at the frontier between metrology and defectivity field is expected to bring solutions for certain types of process deviation. In our case, ellipsometry’s optical response was collected on large areas of product wafers to capture specific deviations such as film properties, thickness, and patterning variation. This is an innovative strategy that relies on a model-less approach to detect process drifts, using ellipsometry’s sensitivity to material properties and design architecture variations. In this paper, we will present this approach on three industrial cases. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing processes, yield analysis aims to increase the yield by determining and managing the causes of low yield. The variable data collected from semiconductor manufacturing processes, in which hundreds of unit processes are implemented according to specific conditions and sequences, are interdependent, and the variables related to previous processes influence the variables in subsequent processes. Therefore, the order of processes should be considered when building a model that searches for the causes of low yield. However, there have been few studies in this area. This paper proposes a low-yield root cause search method considering the order of processes using a long short-term memory with attention mechanism (LSTM-AM) model. Specifically, the LSTM-AM model is applied to data classified according to the process structure of semiconductor products, and the causes of low yield are determined considering the order of processes by extracting attention weights. Experiments are conducted to verify the suitability of the proposed method using real yield data from a semiconductor company. The experimental results confirm that the proposed method outperforms the existing low yield root cause search methods in terms of low yield prediction. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. [ABSTRACT FROM AUTHOR]

Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality. [ABSTRACT FROM AUTHOR]

Wafer bin maps contain vital information that helps semiconductor manufacturers to identify the root causes and defect pattern failures in wafers. Conventional manual inspection techniques in inspecting these failures are labour intensive and cause prolonged production cycle time. Therefore, automatic inspection techniques can solve this problem. This paper proposes a deep learning approach based on deep convolutional generative adversarial network (DCGAN) and a new Capsule Network (WaferCaps). DCGAN was used to upsample the original dataset and therefore increase the data used for training and balance the classes at the same time. While WaferCaps was proposed to classify the defect patterns according to eight classes. The performance of our proposed DCGAN and WaferCaps was compared with different deep learning models such as the original Capsule Network (CapsNet), CNN, and MLP. In all of our experiment, WM-811K dataset was used for the data upsampling and training. The proposed approach has shown an effective performance in generating new synthetic data and classify them with training accuracy of 99.59%, validation accuracy of 97.53% and test accuracy of 91.4%. [ABSTRACT FROM AUTHOR]

Detecting defects in the inspection stage of semiconductor manufacturing process is a crucial task to improve yield and productivity as well as wafer quality. Recent Advances in semiconductor process technology have greatly increased the transistor density. As a result, an increasingly high number of defects inevitably emerge and we need a more accurate and efficient detection method to manage them. In this paper, we propose a deep-learning-based defect detection model to expedite the process. It adopts an adversarial network architecture of conditional GAN. The discriminator of an adversarial network architecture helps the detection model learn to detect and classify defects accurately. The high performance is achieved by using Focal Loss, PixelGAN and multi-scale level features, which is shown to be better than the baseline model, CenterNet, when tested for a real industrial dataset. [ABSTRACT FROM AUTHOR]

A wafer bin map (WBM) represents the wafer testing results for individual dies on a wafer using a binary value that represents pass or fail. WBMs often have specific defect patterns, which occur because of assignable causes. Therefore, the identification of defect patterns in WBMs aids in understanding the root causes of process failure. Previous studies on the classification of WBM defect patterns have demonstrated effective performances. However, in previous studies, the effect of class imbalance on the WBM defect patterns was not considered, although in practice, it is more reasonable to assume that there is a significantly large number of WBMs that lack defect patterns because they occur when there are process faults. In this paper, we propose memory-augmented convolutional neural networks with triplet loss for classifying defect patterns in highly imbalanced WBM data. We use a triplet loss-based convolutional neural network as an embedding function to obtain a well-separated low-dimensional space according to the defect patterns. We then use a memory module to balance the number of WBMs between defect-pattern classes. We train the proposed model end-to-end to learn the embedding function and update the memory simultaneously. We then validate the proposed model using simulated WBM data. The proposed model demonstrates a high classification performance and effective embedding results for imbalanced WBM data. [ABSTRACT FROM AUTHOR]

We present a new set of simulation models, organized in a testbed. The aim of the testbed consists in providing researchers with a platform able to credibly represent the complexity of modern semiconductor manufacturing. The testbed is open to public use, and include so far four models. A high-volume/low-mix model and a low-volume/high-mix model constitutes the foundation of the testbed. Two additional models incorporate the complexity of engineering lots. We conclude this paper by presenting a case study that demonstrates that the third and fourth model can be used to assess the performance of integrated dispatching strategies for production and engineering lots. [ABSTRACT FROM AUTHOR]

In this paper, a qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is studied. The stepper machines, a common bottleneck in many wafer fabs, must be qualified to process lots of different families. A qualification time window is associated with each stepper and family. It can be reinitialized as needed and can be extended by on-time processing of lots from qualified families. Fast heuristic approaches, among them a Greedy Randomized Adaptive Search Procedure (GRASP), are proposed to solve large-sized problem instances using a small amount of computing time. The qualification decisions modeled by binary decision variables are made by heuristic procedures that exploit the problem structure while the real-valued quantities for each family and stepper are computed using linear programming. Computational experiments based on randomly generated problem instances are conducted. The results show that the proposed matheuristics are able to quickly provide high-quality solutions. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturers aim to fabricate defect-free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and faults during the fabrication process. Machine learning (ML) methods have been used to classify these defects in order to locate the root causes of failure. This paper proposes a novel deep-structured ML approach as an extension of our previous randomized general regression network (RGRN) model, to identify and classify both single-defect and mixed-defect patterns. The principal motivation for this paper is that a shallow-structured RGRN performs well on single-pattern defects, achieving an accuracy of 99.8%, but performs poorly when a wafer has mixed-defect patterns. The proposed approach improves RGRN performance, particularly on mixed-pattern defects, by incorporating a novel information gain (IG)-based splitter as well as deep-structured ML. A spatial filter is applied to remove random noise and reduce model bias during training. During the first detection stage, the splitter generates unique rules that are built using the IG theory and splits the defects data into single-defect and mixed-defect patterns. Single-defect patterns are then classified by RGRN, whereas mixed-defect patterns are fed into the deep-structured ML model for further classification. This combination improves the ability of the proposed approach to classify diverse defect patterns and achieve a better overall performance. Our experimental results demonstrate that the proposed approach achieves an overall detection accuracy of 86.17% on a dataset that contains real data representing both single-defect and mixed-defect patterns, as commonly found in real manufacturing scenarios, outperforming existing ML-based models. [ABSTRACT FROM AUTHOR]

A hybrid multirobot cluster tool is composed of both single and dual-arm robotic cluster tools. Since the behavior of different individual tools is different, it is very challenging to coordinate their activities in such a tool and to schedule it optimally. To find a one-wafer cyclic schedule to reach the shortest cycle time for a treelike hybrid multirobot cluster tool whose bottleneck tool is process-bound, this paper extends resource-oriented Petri nets to model it such that a schedule can be parameterized by its robots’ waiting time. Based on the model, this paper then establishes the conditions under which there is a one-wafer cyclic schedule such that the shortest cycle time can be obtained. An efficient algorithm is also given to test the existence of such a schedule and to find it if existing. At last, examples are used to illustrate the proposed approaches. [ABSTRACT FROM AUTHOR]

Scheduling a multicluster tool with wafer residency time constraints is highly challenging yet important in ensuring high productivity of wafer fabrication. This paper presents a method to find an optimal one-wafer cyclic schedule for it. A Petri net is developed to model the dynamic behavior of the tool. By this model, a schedule of the system is analytically expressed as a function of robots’ waiting time. Based on this model, this paper presents the necessary and sufficient conditions under which a feasible one-wafer cyclic schedule exists. Then, it gives efficient algorithms to find such a schedule that is optimal. These algorithms require determining the robots’ waiting time via simple calculation and thus are efficient. Examples are given to show the application and effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Quality inspection in semiconductor manufacturing is of great importance in the modern industries. In the recent years, intelligent data-driven condition monitoring methods have been successfully developed and applied in the industrial applications. However, despite the promising condition monitoring performance, the existing methods generally assume the training and testing data are from the same distribution. In practice, due to variations in manufacturing process, the collected data are usually subject to different distributions in different operating conditions, that significantly deteriorates the performance of the data-driven methods. To address this issue, this paper proposes a deep learning-based domain adaptation method for fault diagnosis in semiconductor manufacturing. The maximum mean discrepancy metric is optimized on the learned high-level data representation in the deep neural network. Experimental results on a real-world semiconductor manufacturing dataset suggest the proposed method offers an effective and generalized data-driven fault diagnosis approach for quality inspection. [ABSTRACT FROM AUTHOR]

Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes. Semiconductor engineers apply various methods for wafer defect classification such as manual visual inspection or machine learning-based algorithms by manually extracting useful features. However, these methods are unreliable, and their classification performance is also poor. Therefore, this paper proposes a deep learning-based convolutional neural network for automatic wafer defect identification (CNN-WDI). We applied a data augmentation technique to overcome the class-imbalance issue. The proposed model uses convolution layers to extract valuable features instead of manual feature extraction. Moreover, state-of-the-art regularization methods such as batch normalization and spatial dropout are used to improve the classification performance of the CNN-WDI model. The experimental results comparison using a real wafer dataset shows that our model outperformed all previously proposed machine learning-based wafer defect classification models. The average classification accuracy of the CNN-WDI model with nine different wafer map defects is 96.2%, which is an increment of 6.4% from the last highest average accuracy using the same dataset. [ABSTRACT FROM AUTHOR]

Manufacturing productivity in the semiconductor industry is a key factor in determining the competitiveness of manufacturers. In order to enhance productivity, evaluating the productivity of wafer maps prior to production and optimizing the productivity of wafer maps is one of the most effective solutions. The productivity of a wafer map is evaluated in advance by considering various factors affecting wafer productivity such as: gross dies, shot counts, lithography throughputs, mask field occupancy (MFO), prices, etc. Manufacturing process information is not determined at the initial wafer map design stage. Predicting the yield of new wafer maps before fabrication is a difficult challenge due to lack of process information. However, a yield prediction model is required to precisely evaluate the productivity of new wafer maps, because the yield is directly related to the productivity and the design of wafer map affects the yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies on a wafer and die-level yield variations collected from a wafer test without process parameters. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach helps to design wafer maps with up to 8.59% higher productivity. [ABSTRACT FROM AUTHOR]

Modeling of dynamic manufacturing processes with slow drift using data-driven approaches is challenging because most data-driven models are trained by off-line data. In this paper, we propose to track slow drift of manufacturing processes using an online Bayesian Auto-Regression eXogenous (ARX) model with time-variant parameters. The model parameters are trained off-line and are updated online using Bayes’ rule. To avoid the frequent online model update, a Sample Importance (SI) test is proposed to screen online samples and only the sample that passes SI test is incremented to the VM model. The SI test decides the importance of the sample by collectively considering sample freshness, model prediction error and prediction uncertainty. Furthermore, the SI test is applied to off-line Data Base (DB) and an iteration algorithm is devised for off-line sample selection. The off-line sample selection algorithm can effectively reduce the sample redundancy in off-line DB while maintaining the model performance. To validate the effectiveness of the proposed method, Prognostics and Health Management (PHM) data challenge 2016 dataset is employed to predict material removal rate of chemical-mechanical planarization process. The validation results indicate that the proposed method outperforms existing state-of-art approaches in literature such as Just-in-Time (JIT) and deep learning models. [ABSTRACT FROM AUTHOR]

Wafer map defect pattern contains the critical information about semiconductor manufacturing, effective defect analysis technology can improve the yield of products. This paper develops a wafer defect pattern recognition and analysis method based on convolutional neural network (CNN). We build an 8-layer CNN model to inspect wafer map defect and a 13-layer model to classify defect patterns. To analyze the defects, we first extract features based on the classification network, then perform PCA dimensionality reduction and similarity ranking, we infer the root causes of tested samples according to the retrieved wafer maps. In particular, we analyze the impacts of different network layers and feature dimensions on image retrieval performance, it turns out that the appropriate dimensionality reduction can increase the accuracy and speed of wafer map retrieval. The models are trained and tested on the WM-811K wafer map dataset, which are collected from real wafer maps. The experimental results show that the proposed method is able to identify common wafer defect patterns and analyze the root causes accurately and effectively. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) predicts the actual measurement for ongoing semiconductor process. Optical emission spectroscopy (OES) data is often used to build up VM models, since it has a lot of information on process quality. However, it also includes significant redundant information, so it is important how to select only meaningful features. Deep learning (DL) techniques have been very successful in analyzing image data and it is tempting to apply those techniques to the OES data. In this paper, we propose DL configurations specific to OES data that outperform those used for image analysis. Specifically, our proposed method accounts for variable size data, chamber to chamber differences, condition drift due to accumulation, observation data drift due to an accumulation of deposition on a window, and the effects of maintenance. We evaluated our method on a real, mass-production dataset and compared our results with those obtained by using state-of-the-art image analysis DL techniques in the famous contest, ImageNet large-scale visual recognition challenge (ILSVRC). [ABSTRACT FROM AUTHOR]

The detection of wafer faults in early process steps through monitoring and analyzing multivariate process trace data contribute to wafer yield improvements. Standard classification algorithms have been generally used for fault detection and classification (FDC). However, this approach can cause information loss while extracting statistical features from the trace data and cannot consider class imbalance situations where much fewer faulty wafers are generated than normal wafers. In addition, the approach does not consider normal wafer-to-wafer (W2W) variations and sensor noise inherent in the trace data. These drawbacks significantly degrade FDC performance. This paper proposes a method that builds an FDC model only with trace data of normal wafers in which W2W variations and sensor noise exist. The one-class FDC method detects the occurrence of abnormal trace patterns that cause wafer faults by removing W2W variations and sensor noise from raw traces by using denoising autoencoders, and this method finds the fault-introducing process parameters with the occurrence times. In experiments using the trace data of etch and chemical vapor deposition processes, the proposed method exhibited 1% and 6% higher performance than the best-performing method among comparison methods in terms of the geometric mean of the normal and fault detection accuracies. [ABSTRACT FROM AUTHOR]

Wafer revisiting and residency time constraints complicate the scheduling problem of cluster tools in semiconductor manufacturing. Random disturbance to the activity time in operating a tool further complicates such a scheduling problem. To solve this challenging problem, this paper proposes a robust real-time schedule which consists of a real-time controller (RTC) and an off-line schedule. The former is developed to offset the activity time disturbance such that the wafer sojourn time fluctuation in a process module is minimized. With the RTC, to find the off-line schedule, necessary and sufficient schedulability conditions under which a feasible schedule exists are derived and these conditions can be easily checked. Then, the off-line schedule can be efficiently found by the proposed algorithms based on nondisturbed activity time if a feasible schedule exists. With the obtained real-time schedule, it is shown that the productivity of the system is maximized. Finally, examples are used to illustrate the proposed approach. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing is a highly innovative branch of industry, where a high degree of automation has already been achieved. For example, devices tested to be outside of their specifications in electrical wafer test are automatically scrapped. In this paper, we go one step further and analyze test data of devices still within the limits of the specification, by exploiting the information contained in the analog wafermaps. To that end, we propose two feature extraction approaches with the aim to detect patterns in the wafer test dataset. Such patterns might indicate the onset of critical deviations in the production process. The studied approaches are: 1) classical image processing and restoration techniques in combination with sophisticated feature engineering and 2) a data-driven deep generative model. The two approaches are evaluated on both a synthetic and a real-world dataset. The synthetic dataset has been modeled based on real-world patterns and characteristics. We found both approaches to provide similar overall evaluation metrics. Our in-depth analysis helps to choose one approach over the other depending on data availability as a major aspect, as well as on available computing power and required interpretability of the results. [ABSTRACT FROM AUTHOR]

In a cluster tool for semiconductor manufacturing, a wafer waits within a chamber after processing until it is unloaded by the robot. Such wafer delays degrade wafer quality due to residual gases and heat, even cause quality failures. A cluster tool mostly operates in a ${K}$ -cyclic schedule, where an identical timing pattern repeats for each ${K}$ cycles, because of sporadic disruptions in process times or robot task times and the closed-architecture of the tool scheduler. In addition, it is hard to predict the ${K}$ -cyclic schedule that the tool will reach. Such a ${K}$ -cyclic schedule makes wafer delays at each chamber repeat ${K}$ different values. Therefore, such variability of wafer delays increases the risk of quality failure. Therefore, we examine the maximum wafer delay among all possible ${K}$ -cyclic schedules called the worst-case wafer delay in this paper. We first characterize the maximum cyclicity ${K}$ of tool schedules. We then develop closed-form formulas for most frequently used wafer flow patterns and an optimization model that computes the worst-case wafer delay. We also identify factors that affect the worst-case wafer delay and their influences by experiments. Finally, we suggest tool operation guidelines for lowering the worst-case wafer delay. [ABSTRACT FROM AUTHOR]

A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. In this paper, we propose a voting ensemble classifier with multi-types features to identify wafer map defect patterns in semiconductor manufacturing. Our research contents can be summarized as follows. First, three distinctive features such as density-, geometry-, and radon-based features were extracted from raw wafer images. Then, we applied four machine learning classifiers, namely logistic regression (LR), random forests (RFs), gradient boosting machine (GBM), and artificial neural network (ANN), and trained them using extracted features of original data set. Then their results were combined with a soft voting ensemble (SVE) technique which assigns higher weights to the classifiers with respect to their prediction accuracy. Consequently, we got performance measures with accuracy, precision, recall, ${F}$ -measure, and AUC score of 95.8616%, 96.9326%, 96.9326%, 96.7124%, and 99.9114%, respectively. These results show that the SVE classifier with proposed multi-types features outperformed regular machine learning-based classifiers for wafer maps defect detection. [ABSTRACT FROM AUTHOR]

Robotized cluster tools for semiconductor wafer fabrication may have a wafer wait within a processing chamber after processing there until the wafer is unloaded from the chamber by a robot. Such wafer delays cause wafer quality degradation or variability due to residual gases and heats within the chamber. There have been numerous works on characterizing wafer delays and scheduling under upper limits on wafer delays while presuming that the tools are operated by well-known simple robot task sequences such as swap or backward sequences. However, when the wafer delay constraints are tight, there may not be feasible schedules for such sequences. We wish to know whether there can be alternative robot task sequences which can satisfy such tight wafer delay constraints. In this paper, we identify a new class of robot task sequences that can better satisfy tight wafer delay constraints than the conventional swap or backward sequences while keeping the same minimum tool cycle time. By examining the circuits of timed event graph (TEG) models for the tool operation behaviors in many different robot task sequences, we identify that such robot task sequences do not make interferences between the work cycles of the resources such as the robot and chambers. The resource interference can cause delays in the work cycles, and hence increase the wafer delays or the tool cycle time. To prove this, we examine circuits in an extended TEG model, a negative event graph, which incorporates time constraints as negative places and tokens. From this, we derive closed-form conditions for which such sequences are feasible against given wafer delay constraints. By experiments, we show that the proposed new sequences have shorter wafer delays, and hence better satisfy tight wafer delay constraints than conventional sequences. Note to Practitioners—As circuit widths shrink down to several nanometers, cluster tools for semiconductor fabrication require extreme process quality control. Even wafer delays within processing chambers of cluster tools can cause wafer quality degradation and variability. Therefore, it is desirable for cluster tools to have much shorter wafer delays. However, conventional sequences such as the swap and backward sequences, which are being prevalently used in practice, may not satisfy tight wafer delay constraints. Our proposed sequences, which are as simple as the conventional sequences, have much shorter wafer delays while keeping the same minimum tool cycle time. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, a wafer bin map (WBM) represents the results of wafer testing for dies using a binary pass or fail value. For WBMs, defective dies are often clustered into groups of local systematic defects. Determining their specific patterns is important, because different patterns are related to different root causes of failure. Recently, because wafer sizes have increased and the process technology has become more complicated, the probability of observing mixed-type defect patterns, i.e., two or more defect patterns in a single wafer, has increased. In this paper, we propose the use of convolutional neural networks (CNNs) to classify mixed-type defect patterns in WBMs in the framework of an individual classification model for each defect pattern. Through simulated and real data examples, we show that the CNN is robust to random noise and performs effectively, even if there are many random defects in WBMs. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) is often applied in semiconductor manufacturing when process measurements cannot be obtained without delay or without impacting the cycle time. When the process condition is varying, the modeling results can be inaccurate if a single VM model is adopted. Also, the large number of variables in the process data increases the difficulty of obtaining good predictions. To improve the accuracy of the metrology value prediction, it is necessary to select and apply only the significant variables in modeling. This paper proposes a just-in-time approach for VM modeling, along with a variable shrinkage and selection method that uses Gaussian process regression. The proposed method is validated using semiconductor process data and found to be superior compared to conventional methods. [ABSTRACT FROM AUTHOR]

A multi-cluster tool is composed of a number of individual cluster tools linked by buffering modules (BMs). The capacity of a BM can be one or two. Aiming at finding an optimal one-wafer cyclic schedule, this paper explores the effect of two-space BMs on the performance of a multi-cluster tool. A Petri net (PN) model is developed to model it by extending resource-oriented PNs. The dynamic behavior of robot waiting and tasks, process modules, and buffers is well described by the model. This paper shows that there is always a one-wafer cyclic schedule that reaches the lower bound of the cycle time of a process-bound tool. Furthermore, a closed-form algorithm is revealed to find such a schedule for the first time for such multi-cluster tools. Illustrative examples are given to show the application and power of the proposed method. [ABSTRACT FROM AUTHOR]

Due to the different behavior of single-arm and dual-arm cluster tools, it is challenging to schedule a hybrid multi-cluster tool containing both of them. This paper aims to find an optimal one-wafer cyclic schedule for such a multi-cluster tool. It is assumed that the bottleneck individual cluster tool in it is process-bound, thereby making it process-dominant. To do so, this paper models a hybrid multi-cluster tool with Petri nets. With this model, it derives the conditions under which individual cluster tools can operate in a paced way. Based on these conditions, this paper shows that for any process-dominant hybrid multi-cluster tool there is always a one-wafer cyclic schedule. Then, it develops the algorithms to find the minimal cycle time and the optimal one-wafer cyclic schedule. It is computationally efficient and easy-to-implement in practice. Examples are given to show the application and effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, with the shrinking down of wafer circuit widths, a strict quality control is required for wafer fabrication processes, resulting in that after a wafer being processed and removed from a chamber, a cleaning operation that takes significant time is performed for eliminating the chemical residual. Such a cleaning operation makes a traditional backward strategy for single-arm cluster tools inefficient. By the existing studies, it is shown that the productivity can be improved if some numbers of chambers at a step are kept empty. With this idea, an extended backward strategy is proposed by deciding the optimal number of empty chambers. Based on such a strategy, this paper studies the challenging problem for scheduling a single-arm cluster tool with both chamber cleaning operations and wafer residency time constraint for the first time. By building a timed Petri net model for the system, two linear programs are proposed to determine the minimal cycle time and test the existence of a feasible schedule and find it if existing. At last, two industrial examples are used to demonstrate the obtained results. [ABSTRACT FROM AUTHOR]

A robotic cluster tool involves many activities whose time is subject to some disturbance, thus leading to the activity time variation. It results in wafer sojourn time fluctuation in a process module, which may in turn violate wafer residency time constraints. Some wafer fabrication requires a revisiting process. With wafer revisiting, the effect of activity time variation on wafer sojourn time fluctuation is so complicated that no analysis was reported to the best knowledge of the authors. It is vitally important to accurately analyze it. To do so, this paper adopts a Petri net model to describe the dynamical behavior of cluster tools. With this model, a real-time control policy is proposed to offset the effect of the activity time variation on wafer sojourn time fluctuation as much as possible. Then, the wafer sojourn time delay is analyzed and algorithms are developed to calculate its exact upper bound. With the proposed method, one can check if a given schedule is feasible under bounded activity time variation. Some practical examples are given to show the application of the proposed approach. [ABSTRACT FROM PUBLISHER]

Accurate prediction of cycle time (CT) plays an important role in the promises of a good delivery-time for semiconductor manufacturers. However, the CTs of wafer lots are difficult to forecast since they are influent by a lot factors (e.g., workload for every machine). The identification of key factors (called CT-related) can not only improve the prediction performance but also facilitate the control of CT, which is of particular significance. This paper focuses on gathering subtle variables into the candidate variables set along with the further analysis which is required in the correlation analysis between various candidate factors and CTs of wafer lots. The candidates set is first constructed to collect all factors that may affect wafer lots’ CT. Then, a regression-based model is proposed to select CT-related variables, which consists of three parts: 1) discretization; 2) adaptive logistic regression-based correlation analysis; and 3) CT-related factor selection. Subsequently, a parallel computation model is implemented to forecast the CTs of wafer lots. In the numerical experiments, 108 CT-related factors stood out from 774 candidates and replaced six global factors (used as reference) to predict CTs of wafer lots. The results indicated that the proposed approach had higher accuracy than linear regression and back propagation network in CT forecasting in large scale data analysis. [ABSTRACT FROM PUBLISHER]

Identifying defect patterns on wafers is crucial for understanding the root causes and for attributing such patterns to specific steps in the fabrication process. We propose in this paper a system called Dominant Defective Patterns Finder (DDPfinder) that clusters the patterns of defective chips on wafers based on their spatial dependence across wafer maps. Such clustering enables the identification of the dominant defect patterns. DDPfinder clusters chip defects based on how dominant are their spatial patterns across all wafer maps. A chip defect is considered dominant, if: 1) it has a systematic defect pattern arising from a specific assignable cause and 2) it displays spatial dependence across a larger number of wafer maps when compared with other defects. The spatial dependence of a chip defect is determined based on the contiguity ratio of the defect pattern across wafer maps. DDPfinder uses the dominant chip defects to serve as seeds for clustering the patterns of defective chips. This clustering procedure allows process engineers to prioritize their investigation of chip defects based on the dominance status of their clusters. It allows them to pay more attention to the ongoing manufacturing processes that caused the dominant defects. We evaluated the quality and performance of DDPfinder by comparing it experimentally with eight existing clustering models. Results showed marked improvement. [ABSTRACT FROM PUBLISHER]

Equipment productivity in semiconductor manufacturing has become a major topic due to high equipment prices. It is easier and more precise to calculate productivity based on the running logs; however, engineers may often be assigned to estimate the productivity of the equipment in the design phase to predict project benefits so that investment decisions can be made. In such situations, no running log is available to calculate equipment productivity. If the architecture of the equipment and the wafer flow are simple, equipment productivity still can be evaluated using algebra-based solutions. Unfortunately, with rapidly shrinking IC dimensions equipment architecture becomes more and more complicated so a linear platform is typically used. In a linear platform, multiple mainframes are used to install more chambers. In each main-frame, there may be multiple robots to enable efficient wafer transmission. It is very difficult to estimate the productivity of a linear platform using simple algebra-based solutions; however, accurate productivity estimation of a linear platform is critical due to its higher price. To address this problem, a novel estimative methodology is proposed in this paper. This method analyzes the potential wait time of a chamber and then identifies the productivity bottleneck of the platform. The proposed methodology is designed for calculating wafers per hour for the linear platform. The accuracy of the proposed methodology is then verified by a simulation model. By applying this methodology to estimate the productivity for a semiconductor manufacturing line incorrect equipment investment can be reduced, therefore enhancing market competitiveness. [ABSTRACT FROM AUTHOR]

In this paper, we focus on yield analysis task where engineers identify the cause of failure from wafer failure map patterns and manufacturing histories. We organize yield analysis task into the following three stages, namely, failure map pattern monitoring, failure cause identification, and failure recurrence monitoring, and incorporate machine learning and data mining technologies into each stage to support engineers’ work. The important point is that big data analysis enables comprehensive and long-term monitoring automation. We make use of fast and scalable methods of clustering and pattern mining and realize daily comprehensive monitoring with massive manufacturing data. We also apply deep learning, which has been an innovative core technology of machine learning in recent years, to classification of wafer failure map patterns, and explore its performance in detail. Finally, these machine learning and data mining techniques are integrated into an automated monitoring system with interfaces familiar to engineers to attain large yield enhancement. [ABSTRACT FROM AUTHOR]

Multi-cluster tools are automated equipment which is increasingly used in semiconductor manufacturing. The scheduling of multi-cluster tools is much more challenging than single-cluster tools due to multi-robot coordination and increasing chambers. In this paper, we develop a mixed integer programming (MIP) model which manages to formulate the multi-robot coordination for cyclic scheduling of multi-cluster tools. Three reformulations of the model are implemented: 1) linearization; 2) eliminating integer variables; and 3) tightening constraints. The first reformulation is designed to make the MIP model solvable by commercial solvers while the other two are intended for promoting computational efficiency which is critical when chambers increase. The proposed model can meet various practical scheduling requirements such as dual-armed robots, wafer residency time constraints, parallel and reentrant processes in multi-cluster tools. Experimental results demonstrate the efficiency of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a supply chain simulation testbed for the semiconductor industry is proposed. We start by identifying requirements for such reference datasets, and then we identify the main building blocks. The nodes of the supply chain that represent semiconductor wafer fabrication facilities (wafer fabs) are built on a simulation model from the measurement and improvement of manufacturing capacity project. We present two techniques to reduce the modeling and computational burden that are able to deal with load-dependent cycle times in single front-end and back-end facilities and in the overall network. The first method models in detail only the bottlenecks in the nodes of the supply chain, while the second one uses empirical distributions for cycle time and throughput. The quality of these reduction techniques is assessed by comparing the detailed model and the models with a reduced level of detail. We present an application scenario for the testbed by simulating a semiconductor supply network. In addition, the usage of the testbed is discussed. [ABSTRACT FROM PUBLISHER]

Many studies on the prediction of manufacturing results using sensor signals have been conducted in the field of fault detection and classification (FDC) for semiconductor manufacturing processes. However, fault diagnosis used to find clues as to root causes remains a challenging area. In particular, process monitoring using neural networks has been employed to only a limited extent because it is a black box model, making the relationships between input data and output results difficult to interpret in actual manufacturing settings, despite its high classification performance. In this paper, we propose a convolutional neural network (CNN) model, named FDC-CNN, in which a receptive field tailored to multivariate sensor signals slides along the time axis, to extract fault features. This approach enables the association of the output of the first convolutional layer with the structural meaning of the raw data, making it possible to locate the variable and time information that represents process faults. In an experiment on a chemical vapor deposition process, the proposed method outperformed other deep learning models. [ABSTRACT FROM PUBLISHER]

Under the trend of globalization, rapid advancement of Information Technology, shorter electronic product life cycles, and the rise of consumer consciousness, there is fiercer market competition in most industries, especially in the semiconductor industry. Effective supply chain management is a critical successful factor for enterprises to survive in such a competitive market since it can help enterprises in reducing cost and improving operational efficiency. For an integrated device manufacturer (IDM) in the semiconductor industry, due to its complex network, strategic alliance among partners as well as supply chain integration are efficient approaches to enhance competitiveness and make more profit. In this paper, we develop an integrated model of supply chain planning for IDMs. The integrated model is developed to help decision makers determine the production quantities and delivery quantities at various locations, the decoupling point of a push–pull supply chain, the inventory buffer at the boundary and the vendor managed inventory scenario. The semiconductor manufacturing characteristics including binning, substitution, and yield are taken into consideration in the formulated model. In addition, the model is developed for a semiconductor supply chain characterized by multiple stages, plants, products, and product grades. [ABSTRACT FROM PUBLISHER]

In semiconductor manufacturing, there are wafer fabrication processes with wafer revisiting. Some of them must meet wafer residency time constraints. Taking atomic layer deposition (ALD) as a typical wafer revisiting process, this paper studies the challenging scheduling problem of single-arm cluster tools for the ALD process with wafer residency time constraints. It is found that there are only several scheduling strategies that are applicable to this problem and one needs to apply each of them to decide whether a feasible schedule can be found or not. This work, for each applicable strategy, performs the schedulability analysis and derives the schedulability conditions for such tools for the first time. It proposes scheduling algorithms to obtain an optimal schedule efficiently if such conditions are met. It finally gives illustrative examples to show the application of the proposed concepts and approach. [ABSTRACT FROM PUBLISHER]

Traditional variables control charts assume that process data is independently identically normally distributed (IIND). Some real-world processes, however, do not obey this convenient assumption. The semiconductor industry is very familiar with non-IIND distributions. The batch processes in the semiconductor manufacturing involve nested variation sources. The variation sources are between-batch variation, the within-batch (or between-wafers) variation in each batch, and the within-wafer variation in each wafer. First, it is proved that the application of traditional mean control chart in the batch process would result in too many false alarms. In addition, some kinds of control charts proposed in previous studies either cannot be used to monitor all the three variation sources or contain too many control charts. In this paper, we propose a new control chart named as two-level nested control chart, composing of four control charts for synthetically monitoring the batch process, which can monitor all the three variation sources. Finally, it was proved by practical application in the process of phosphorus diffusion that this new control chart can be used to monitor all the three variation sources of batch processes. [ABSTRACT FROM AUTHOR]

In recent years, the semiconductor manufacturing industry has recognized class imbalance as a major impediment to the development of high-performance fault detection (FD) models. Class imbalance refers to skews in class distribution in which normal wafer samples are considerably more abundant than fault samples. In such a situation, standard machine learning algorithms create FD models with classification boundaries that are biased toward majority-class data, resulting in high type II error rates. In this paper, we compare the performance of machine learning algorithms for class-imbalanced FD problems. We evaluate the performance of three sampling-based algorithms, four ensemble algorithms, four instance-based algorithms, and two support vector machine algorithms. Two experiments were conducted to compare algorithm performance using etching process data and chemical vapor deposition process data. Different data scenarios were considered by setting the imbalance ratio to three levels. The results of the experiments indicated that the instance-based algorithms presented excellent performance even when the imbalance ratio increased. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) has been successfully applied to semiconductor manufacturing as an efficient way of achieving wafer-to-wafer quality control. VM involves the estimation of metrology variables of wafer inspection using a prediction model trained with process parameters and measurements prior to the actual implementation of metrology. VM modeling should incorporate a number of process parameters and measurements collected from each piece of process equipment, which results in a greater number of input variables. Therefore, it is necessary to resolve the problem of high dimensionality through feature selection. A suitable feature selection method for VM modeling should effectively address the high dimensionality by lowering the computational cost, while also achieving high prediction accuracy as an essential requirement for the practical deployment of VM. In this paper, a feature selection method based on random forward search is proposed for efficient VM modeling. This method selects relevant variables sequentially from disjoint random subsets of candidate variables by incorporating randomness. Our preliminary experimental results obtained with real-world semiconductor manufacturing data demonstrate that the proposed feature selection method achieves comparable prediction accuracy yet has the advantages of being computationally more efficient, thus merits further investigation. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing, production ramp-up is a necessary phase before a new technology is introduced because it affects not only the time-to-market, but also the time-to-volume (the time to reach mass production). In production ramp-up, engineering lots are implemented in order to collect data for product and equipment qualification, and they are expected to achieve short cycle times (CTs) and high throughputs. On one hand, the increment of the amount of engineering lots will disrupt the smoothness of the manufacturing flow and cause work-in-process (WIP) bubbles. On the other hand, to ensure the feasibility of the production plan, some throughput and CT targets must be achieved. There is a need to determine an appropriate wafer start mix to strike a balance between the conflicting objectives. However, the complexity and stochasticity existing in the semiconductor manufacturing process makes it a very difficult task. This paper modeled the wafer start mix determination problem and proposed an efficient methodology, called progressive simulation optimization (PSO), based on the simulation metamodeling techniques to handle this problem. The goal was to find the optimal wafer start mix that enables maximum throughput of engineering lots, while satisfying the requirement of CT of normal lots (NL). A numerical study was conducted to evaluate the performance of the proposed PSO, and an empirical study based on real data was conducted to validate the viability of the proposed methodology in practice. [ABSTRACT FROM PUBLISHER]

We report on defects characterization and reduction as well as die strength enhancement using stealth dicing (SD) on high-backside reflectance (82%) 2-D NAND memory wafers. This is performed using three-strata subsurface infrared (1.342 ${{\mu } }\text{m}$ ) nanosecond pulsed laser die singulation with a partial-SD before grinding integration approach. In this paper, a combination of simulation, characterization, and optimization of the multi-strata SD process has led to the elimination of mechanical and absorptive laser singulation related defects such as frontside and backside surface ablation, and topside, backside, and edge chipping. At the same time, the kerf width and kerf straightness are robust against the effects of test element structures located along the dicing streets. There is a consistent coverage of high-quality SD kerf production with near-zero kerf loss across the 300 mm wafer. Multi-strata SD-unique defects such as interference effects and inter-strata cleavage plane {111} damage have been addressed. SD-related integrated defects including Si dust residue post-backgrinding and die attach film-related defects post-die separation have also been resolved. We illustrate the performance of this approach by demonstrating defect-free eight die stacks of $25~{{\mu } }\text{m}$ thick memory dies. [ABSTRACT FROM AUTHOR]