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Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges. [ABSTRACT FROM AUTHOR]

To monitor process and identify the deviation as early as possible, data-driven methods have been applied for process monitoring and fault detection in semiconductor manufacturing. Although various fault detection and classification models had been discussed in the literature, however, little research has been devoted to feature selection from trace data that is important for process monitoring of natural variation. Additionally, the high-mix production mode with different recipes leads to process dynamic of wafer-to-wafer (W2W) variation which should also be identified for safeguarding false alarms and serving as a warning indicator. Therefore, this paper proposes a data-driven framework to identify the key features with respect to the W2W variation. In particular, the self-organizing map is used to annotate the grade of wafer variation among the in-line metrology data. Subsequently, the adaptive boosting (AdaBoost) is adopted to examine the effectiveness of every feature and its processing times, respectively. To validate the proposed framework, an empirical study from a semiconductor fabrication plant is conducted. The experimental results demonstrate that the key feature identification is of critical importance to build highly capable models for process monitoring. Through the dimensionality reduction technique, it has been illustrated that a smaller set of the identified key features are able to pinpoint the W2W variation of different wafer grades more clearly than the whole set of process features. Note to Practitioners— Process monitoring has become more difficult with the shrinking linewidth in semiconductor manufacturing. The challenges of analyzing equipment sensor or raw trace data for process monitoring in high-mix manufacturing processes are to incorporate subject-matter expert knowledge for setting control limit meticulously, to detect the subtle changes by analyzing the whole trace data profile, and to identify W2W variation for reducing false alarms. This paper proposes a data-driven framework for process monitoring by adopting data-driven approaches without recourse to domain judgement. Experimental results demonstrate that the proposed data-driven framework can effectively identify the key features via sensor readings and corresponding processing times, respectively. The engineers can make use of the extracted features to perform a predictive monitoring on metrology data for detection of potential process deterioration. [ABSTRACT FROM AUTHOR]

In manufacturing industries, it is of fundamental importance to detect anomalies in production in order to meet the required quality goals and to limit the number of defective products that are accidentally delivered to the customers. Nevertheless, monitoring systems currently employed in production are typically very simple and rely on a set of univariate control charts that fail to capture the multivariate and complex nature of real-world industrial systems. In such context, Machine Learning (ML)-based approaches for Anomaly Detection (AD) have proven to be extremely effective in increasing anomalies detectability and, in general, in enhancing monitoring procedures. However, industrial data are typically very complex and not suitable to be fed directly to classical ML-based AD tools making feature extraction procedures a necessary step that unfortunately may lead to information loss and low scalability. Deep Learning, has proven very effective at learning useful representations of complex data in an automatic way. In this paper, we propose an AD pipeline that makes use of convolutional autoencoders to extract useful features from two-dimensional, non-image, data. We test our approach on real world Optical Emission Spectroscopy data that are typical of semiconductor manufacturing and we achieve improved performance over classical monitoring methods. Note to Practitioners—Advanced monitoring is one of the most important task in the context of Industry 4.0. Some of the main issues in developing Machine Learning-based solutions in industrial environment are: (i) the lack of reliable tagged data; (ii) the complexity of data structures present in real-world scenarios. In this paper we investigate unsupervised anomaly detection for 2-dimensional data in manufacturing environment: we provide an approach that exploit Deep Learning-based architecture for handling the data at hand. We show the effectiveness of the proposed approach in a real world case study related to optical emission spectroscopy data in semiconductor manufacturing process providing satisfactory classification accuracy. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing consists of multiple sequential processes. In addition, even in a single process, a wafer must pass several steps. Accordingly, a dataset generated in semiconductor manufacturing has sequential information. Thus, the sequential information between steps and processes must be considered when predicting a target variable such as a yield or defect status. This paper proposes a method that utilizes the concept of residual learning to capture sequential information. Specifically, we propose to learn several modules that use data gathered starting from different steps and obtain a final decision by combining all modules’ decisions. In each module including multiple models, the first model is trained to predict the target variable using the data from the earliest step, and the remaining models are trained to predict the residuals that cannot be explained by the models for the previous steps based on the concept of residual learning. We conducted extensive experiments using two real-world semiconductor manufacturing datasets and found that even though each module’s performance was not good, the final decision obtained by combining all the modules’ decisions achieved a significant performance improvement. As a result, the proposed method significantly outperformed the baseline models. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. [ABSTRACT FROM AUTHOR]

Data-driven Fault Detection and Classification approaches are becoming increasingly important in semiconductor manufacturing and in other industries aiming at implementing the Zero-defect paradigm. Two of the main challenges in developing such solutions are: (i) the complexity of sensor data, that typically presents themselves in the form of time-series, requiring the employment of time-consuming and possibly sub-optimal feature extraction approaches; (ii) the fact that faults/defects may be caused by more than a single process, but in many cases they are generated by a cascade of processes. In this paper, we tackle the first issue, by considering a two-stage case study consisting of a deposition process and a rapid thermal process. The proposed approach is based on convolutional deep autoencoders employed to perform feature extraction from time-series sensor data in frontend production equipment. We will show on the reported case study, how the proposed approach outperfoms key numbers-based approaches typically used in the industry. To allow reproducibility of the reported results and to foster research in the field, we publicly share the data used in this work. [ABSTRACT FROM AUTHOR]

Semiconductors are essential components in many electronic devices. Because wafers are produced quickly and in large quantities, defects occur that adversely affect semiconductor properties. This makes it necessary to install powerful and robust inspection systems which use artificial intelligence techniques in the early stages of the manufacturing chain in order to detect and classify those defects. This paper proposes a method for defect detection and classification on images of semiconductor wafer materials obtained by means of a scanning electron microscope based in the following stages: (i) use of computer vision techniques to isolate the defect from the background; (ii) use of several descriptors based on shape, size, texture, histogram, and key-points to create a feature vector for the characterization of the defect; (iii) application of an exhaustive search as a feature selection method to determine the optimal subset of feature descriptors; and (iv) evaluation of the feature descriptors by using a support vector machine classifier providing the optimal set with highest F1-score metrics. Finally, the effectiveness of the proposed approach is compared with five popular feature selection methods, reporting better classification results than the latter. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing is on the cusp of a revolution – the Internet of Things (IoT). With IoT we can connect all the equipment and feed information back to the factory so that quality issues can be detected. In this situation, more and more edge devices are used in wafer inspection equipment. This edge device must have the ability to quickly detect defects. Therefore, how to develop a high-efficiency architecture for automatic defect classification to be suitable for edge devices is the primary task. In this paper, we present a novel architecture that can perform defect classification in a more efficient way. The first function is self-proliferation, using a series of linear transformations to generate more feature maps at a cheaper cost. The second function is self-attention, capturing the long-range dependencies of feature map by the channel-wise and spatial-wise attention mechanism. We named this method as self-proliferation-and-attention neural network (SP&A-Net). This method has been successfully applied to various defect pattern classification tasks. Compared with other latest methods, SP&A-Net has higher accuracy and lower computation cost in many defect inspection tasks. [ABSTRACT FROM AUTHOR]

Wafer bin maps contain vital information that helps semiconductor manufacturers to identify the root causes and defect pattern failures in wafers. Conventional manual inspection techniques in inspecting these failures are labour intensive and cause prolonged production cycle time. Therefore, automatic inspection techniques can solve this problem. This paper proposes a deep learning approach based on deep convolutional generative adversarial network (DCGAN) and a new Capsule Network (WaferCaps). DCGAN was used to upsample the original dataset and therefore increase the data used for training and balance the classes at the same time. While WaferCaps was proposed to classify the defect patterns according to eight classes. The performance of our proposed DCGAN and WaferCaps was compared with different deep learning models such as the original Capsule Network (CapsNet), CNN, and MLP. In all of our experiment, WM-811K dataset was used for the data upsampling and training. The proposed approach has shown an effective performance in generating new synthetic data and classify them with training accuracy of 99.59%, validation accuracy of 97.53% and test accuracy of 91.4%. [ABSTRACT FROM AUTHOR]

Searching for and comparing similar wafer maps can provide crucial information for root cause analysis in the manufacturing process of integrated circuits. Owing to the high dimensionality and complexity of defect patterns, comparison of similar maps in their entirety is inefficient. This paper proposes an automated similarity ranking system with a novel feature set as a reduced representation of wafer maps. To detect systematic failure patterns across wafer maps, we use nonparametric Bayesian clustering based on the Dirichlet process Gaussian mixture model, and hierarchical clustering based on the symmetric Kullback–Leibler divergence. The proposed features are efficient because they require minimal computation and storage; furthermore, they allow for highly discriminative rankings of similar failure patterns. Thus they are suitable for large-scale analysis of wafer maps. The proposed method is experimentally verified using a real wafer map dataset from a semiconductor manufacturing company, and a subset of WM-811K. [ABSTRACT FROM AUTHOR]