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Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This is a panel paper that discusses the use of Artificial Intelligence (AI) technologies to address production and supply chain level problems in semiconductor manufacturing. We have gathered a group of expert semiconductor researchers and practitioners from around the world who have developed AI solutions for various semiconductor problems. This paper aims to provide their answers to an initial set of questions and provide an overview of the AI developments and empirical studies to make suggestions for future directions in this arena. [ABSTRACT FROM AUTHOR]

This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

We are pleased to announce that the June 2022 issue of the IEEE Transactions on Dielectrics and Electrical Insulation (TDEI) will be a special issue on electrets and related phenomena. This issue is open to all authors. Presenters of papers at the IEEE 18th International Symposium on Electrets (ISE18) to be held during September 24–28, 2021 in Shanghai (China) are especially encouraged to submit their work to this special issue. For more information on ISE18 please go to https://ise18.tongji.edu.cn/. [ABSTRACT FROM AUTHOR]

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers. [ABSTRACT FROM AUTHOR]

This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing has been extensively exploiting machine-learning (ML) to process equipment sensory data (ESD) for near-real time anomaly detection (AD). ESD characteristics are highly diversified and data lengths vary among processing steps and cycles. Cleansing ESD with minimum distortion (CMD) to fit the fixed-length input requirement by ML-based AD is critical to AD effectiveness and is challenging. This paper presents a novel CMD method of four innovations: i) statistical mode-based equalization of step data lengths for the least number of step data length changes, ii) importance indicator value (IIV) of a data sample based on its relative difference with the subsequent sample, and iii) step data segmentation into groups based on samples of significant IIVs and the least-entropy-group-to-cleanse-first rule, and iv) cleansing the least IIV sample(s) in the selected group for step data length equalization. CMD application to ESD demonstrates its characteristics preservation property. Simulation experiments are on an integration of data cleansing with an unsupervised ML-based AD system, STALAD. Comparisons with two benchmark methods over AD scenarios of small-scale drifts and shifts show that CMD not only is superior in facilitating accurate detection by STALAD but also helps detect anomaly much earlier than using the two benchmarks. [ABSTRACT FROM AUTHOR]

Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving improved predictive performance by selecting or extracting important variables among high-dimensional variables such as equipment sensor data. However, the management of wafer chip quality requires not only average measurement values but also measurement value predictions for chips located at the edges, which are vulnerable to defects. In this paper, we therefore propose a graph attention (GAT) network-based VM model that predicts the measurement values of chips located at wafer edges by constructing graph data with measurement data (i.e., the measurement location information in wafers and the measurement values). To verify the performance of the proposed model, we conduct a comparative experiment with conventional machine learning methods. The experimental results show that the proposed VM model contributes to a predictive performance improvement in terms of the measurement values of chips located at wafer edges. [ABSTRACT FROM AUTHOR]

The "IEEE Transactions on Semiconductor Manufacturing" is a journal that publishes the latest advancements in the manufacturing of microelectronic and photonic components. It aims to enhance knowledge and improve manufacturing practices in the semiconductor industry. The journal covers various topics such as process integration, manufacturing equipment performance, yield analysis, metrology, and supply chain management. Papers submitted to the journal should focus on practical engineering techniques for solving manufacturing-related problems. The journal follows a peer-review process and encourages authors from low-income countries to submit their work. The standard length for regular papers is eight pages, and shorter contributions can be submitted as letters. The journal provides guidelines for manuscript preparation, including the use of the IEEE template style. It also accepts graphical abstracts and electronic supplements. Authors are responsible for preparing a publication-quality manuscript and may use English language editing services if needed. Plagiarism is strictly prohibited, and manuscripts found to have plagiarized content may be penalized. Authors are required to have an Open Researcher and Contributor ID (ORCID) and can submit their manuscripts online. The journal offers both traditional and open access publication options, with associated fees. Native language author names are supported, and page charges may apply for publication. The IEEE holds the copyright to the published material. [Extracted from the article]

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection. [ABSTRACT FROM AUTHOR]

In current semiconductor manufacturing, limited raw trace data pertaining to defective wafers make fault detection (FD) assignments extremely difficult due to the data imbalance in wafer classification. To mitigate, this paper proposes using a variational autoencoder (VAE) as a data augmentation strategy for resolving data imbalance of temporal raw trace data. A VAE with few defective samples is first trained. By means of extracting the latent variables that characterize the distribution of the defective samples, we make use of the statistical randomness of the latent variables to generate synthesized defective samples via the decoder scheme in the trained VAE. Two data representations and VAE modeling strategies, concatenation of multiple and individual raw trace data as the input of the VAE during the training stage, are investigated. A real-data plasma enhanced chemical vapor deposition (PECVD) process having only few defective samples is used to illustrate the performance enhancement to wafer classification arising from the proposed data augmentation framework. Based on the computational comparisons between noted classification models, the proposed generative VAE model via the individual strategy enables the adaptive boosting (AdaBoost) classifier to achieve perfect performances in every metrics if the 80% and 100% over-sampling ratios are adopted. [ABSTRACT FROM AUTHOR]

Semiconductor vertical furnaces must achieve even faster and more precise temperature control due to the demand for ever-reducing the minimum feature size or critical dimension in semiconductor chips. Also, the insulation performance of vertical furnaces has improved to reduce power consumption; as a side effect, temperature reduction operation takes longer without active cooling. Therefore, in addition to heaters, vertical furnaces equipped with coolers have emerged to achieve higher productivity, more precise temperature control, and lower power consumption. However, the inability to generate positive and negative control inputs for one of the heaters or coolers poses a challenge for an intuitive controller parameter design. The aim of this paper is to address these issues by proposing an intuitive method for designing a controller in the frequency domain which virtually integrates heaters and coolers. We implemented the controller in a full-scale actual semiconductor vertical furnace and first confirmed that the linearity is high. Furthermore, we experimentally verified that the controller achieves both high-speed, high-precision temperature control and low power consumption. [ABSTRACT FROM AUTHOR]

To monitor process and identify the deviation as early as possible, data-driven methods have been applied for process monitoring and fault detection in semiconductor manufacturing. Although various fault detection and classification models had been discussed in the literature, however, little research has been devoted to feature selection from trace data that is important for process monitoring of natural variation. Additionally, the high-mix production mode with different recipes leads to process dynamic of wafer-to-wafer (W2W) variation which should also be identified for safeguarding false alarms and serving as a warning indicator. Therefore, this paper proposes a data-driven framework to identify the key features with respect to the W2W variation. In particular, the self-organizing map is used to annotate the grade of wafer variation among the in-line metrology data. Subsequently, the adaptive boosting (AdaBoost) is adopted to examine the effectiveness of every feature and its processing times, respectively. To validate the proposed framework, an empirical study from a semiconductor fabrication plant is conducted. The experimental results demonstrate that the key feature identification is of critical importance to build highly capable models for process monitoring. Through the dimensionality reduction technique, it has been illustrated that a smaller set of the identified key features are able to pinpoint the W2W variation of different wafer grades more clearly than the whole set of process features. Note to Practitioners— Process monitoring has become more difficult with the shrinking linewidth in semiconductor manufacturing. The challenges of analyzing equipment sensor or raw trace data for process monitoring in high-mix manufacturing processes are to incorporate subject-matter expert knowledge for setting control limit meticulously, to detect the subtle changes by analyzing the whole trace data profile, and to identify W2W variation for reducing false alarms. This paper proposes a data-driven framework for process monitoring by adopting data-driven approaches without recourse to domain judgement. Experimental results demonstrate that the proposed data-driven framework can effectively identify the key features via sensor readings and corresponding processing times, respectively. The engineers can make use of the extracted features to perform a predictive monitoring on metrology data for detection of potential process deterioration. [ABSTRACT FROM AUTHOR]

In manufacturing industries, it is of fundamental importance to detect anomalies in production in order to meet the required quality goals and to limit the number of defective products that are accidentally delivered to the customers. Nevertheless, monitoring systems currently employed in production are typically very simple and rely on a set of univariate control charts that fail to capture the multivariate and complex nature of real-world industrial systems. In such context, Machine Learning (ML)-based approaches for Anomaly Detection (AD) have proven to be extremely effective in increasing anomalies detectability and, in general, in enhancing monitoring procedures. However, industrial data are typically very complex and not suitable to be fed directly to classical ML-based AD tools making feature extraction procedures a necessary step that unfortunately may lead to information loss and low scalability. Deep Learning, has proven very effective at learning useful representations of complex data in an automatic way. In this paper, we propose an AD pipeline that makes use of convolutional autoencoders to extract useful features from two-dimensional, non-image, data. We test our approach on real world Optical Emission Spectroscopy data that are typical of semiconductor manufacturing and we achieve improved performance over classical monitoring methods. Note to Practitioners—Advanced monitoring is one of the most important task in the context of Industry 4.0. Some of the main issues in developing Machine Learning-based solutions in industrial environment are: (i) the lack of reliable tagged data; (ii) the complexity of data structures present in real-world scenarios. In this paper we investigate unsupervised anomaly detection for 2-dimensional data in manufacturing environment: we provide an approach that exploit Deep Learning-based architecture for handling the data at hand. We show the effectiveness of the proposed approach in a real world case study related to optical emission spectroscopy data in semiconductor manufacturing process providing satisfactory classification accuracy. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing consists of multiple sequential processes. In addition, even in a single process, a wafer must pass several steps. Accordingly, a dataset generated in semiconductor manufacturing has sequential information. Thus, the sequential information between steps and processes must be considered when predicting a target variable such as a yield or defect status. This paper proposes a method that utilizes the concept of residual learning to capture sequential information. Specifically, we propose to learn several modules that use data gathered starting from different steps and obtain a final decision by combining all modules’ decisions. In each module including multiple models, the first model is trained to predict the target variable using the data from the earliest step, and the remaining models are trained to predict the residuals that cannot be explained by the models for the previous steps based on the concept of residual learning. We conducted extensive experiments using two real-world semiconductor manufacturing datasets and found that even though each module’s performance was not good, the final decision obtained by combining all the modules’ decisions achieved a significant performance improvement. As a result, the proposed method significantly outperformed the baseline models. [ABSTRACT FROM AUTHOR]

The Czochralski (CZ) process is the core technology for producing semiconductor silicon monocrystalline (SMC), and it is a complex batch process. However, the crystal growth rate and crystal diameter, which are key quality indicators, are difficult to detect directly online, and the offline calculation process lags seriously, which easily causes blind crystal quality control. Therefore, this paper proposes a data-driven and mechanism-based hybrid model for semiconductor SMC quality variables prediction in the CZ process. Firstly, a data-driven model JITL-SAE-ELM based on just-in-time learning (JITL) fine-tuning strategy is proposed. This model is used to solve the nonlinear and time-varying relationship of the energy transfer process in the CZ process that cannot be accurately described by traditional mechanism models. Here, the SAE-ELM model integrates a stacked autoencoder (SAE) and an extreme learning machine (ELM), which are used to deeply capture the nonlinear and time-varying features of process data. Secondly, according to the hydrodynamics and geometric behavior, a crystal pulling dynamic mechanism model based on the crystal growth mechanism is constructed, which avoids the complicated heat transfer link. Further, considering the unmodeled dynamics caused by model parameter uncertainty during the combination of the energy transfer model and crystal pulling dynamic mechanism model, a crystal diameter compensation model SAE-ELM was developed to improve the prediction accuracy of the CZ process hybrid model. Finally, an industrial data experiment based on a CZ monocrystal furnace illustrates the proposed method. [ABSTRACT FROM AUTHOR]

Semiconductor fabrication involves hundreds of process steps through various manufacturing tools. These processing steps are composed of many manufacturing and inspection steps. Inspection is an important step in the fabrication process to determine whether a process is in or out of control. Abrupt manufacturing or inspection tool excursion can lead to a serious low yield problem. Although commonality analysis is a proven tool for detecting abrupt tool excursion, it has gained only limited success in detecting manufacturing tool excursion outside of inspection tools. Compared with manufacturing tools, only a small number of lots or wafers pass through inspection tools. Therefore, it is difficult to construct a sufficient lot history log for inspection commonality analysis in contrast to that of manufacturing tools. Furthermore, inspection may stress a wafer during its own processing, therefore, the target wafer is changed sequentially or randomly. Accordingly, a lot history is apt to include missing traces, which hinders finding inspection tool excursion effectively. In this paper, we propose a comparative analysis framework for commonality analysis algorithms. Performance measures are suggested. To compare the performance of the algorithms effectively, we use a synthetically generated dataset in a simulation experiment. In addition, we apply the algorithms to a real problem that occurred in the fabrication process. Our proposed algorithm demonstrates superiority over the other commonality analysis algorithms in the experiments. [ABSTRACT FROM AUTHOR]

In order to generalize the applicability of Conditional Value at Risk, one of the most widely used measurements used in financial risk management, we develop a solution methodology for the conditional expectation (CE)-based simulation optimization problems. To optimize CE-based objective functions in a highly generalized context, we propose a gradient-free, direct search optimization method, called SNM-CE, which inherits the search framework of Stochastic Nelder-Mead (SNM) Simplex Method but further incorporates effective mechanisms designed for handling problems with CE-based objective functions. As we assume the underlying problem is complicated enough that no closed-form expression can represent the objective function, stochastic simulation is applied to estimate CE. We apply Importance Sampling (IS) as a variance reduction technique, which, combined with a newly-developed methodology, called SOCBA-mn, ensures that simulation resources are used with great efficiency. We show that SNM-CE can converge to the true global optimum with probability one (w.p.1) like SNM. An extensive numerical study and a communication system-based empirical study are both conducted to demonstrate the effectiveness, efficiency and viability of this research in both theoretical and practical settings. Note to Practitioners—This paper develops a direct search algorithm, called SNM-CE, used for solving conditional expectation-based simulation optimization problems. By tackling conditional expectation-based problems, SNM-CE fills a gap in the stochastic optimization literature which has traditionally focused on expectation- or quantile-based objective functions. SNM-CE possesses a high degree of flexibility and generalizability which users can benefit from in solving real-world applications. For example, the $\alpha $ value in the CE-based simulation optimization formulation can be freely adjusted. In other words, the quantile value above which the CE is estimated and optimized can be set according to the needs of the practitioner and/or characteristics of the problem to be solved. Also, SNM-CE is designed such that instead of setting the $\alpha $ value, the user may choose to utilize a particular numerical value of the objective function as the threshold for the CE estimation and optimization. SNM-CE is also simple in terms of implementation and, being a direct search method, does not impose many assumptions about the structure of the underlying objective function and does not necessitate the use of gradient information in the search process. As one application example, SNM-CE can be utilized to select the operational parameters which minimize the average delay in the manufacturing of semiconductors given that the delay exceeds the 90th percentile of simulated delay times. [ABSTRACT FROM AUTHOR]

In semiconductor etching processes, fault detection monitors the quality of wafers. However, the detailed dynamics in batch data are ignored in many traditional methods. In this paper, sequential image-based data visualization and fault detection, using bi-kernel t-distributed stochastic neighbor embedding (t-SNE), is proposed for semiconductor etching processes. In the proposed method, multi-modals, multi-phases, and abnormal samples in batches are visualized in two-dimensional maps. First, the batch data are restructured into sequential images and input to a convolutional autoencoder (CAE) to learn the abstract representation. Then, bi-kernel t-SNE is applied to visualize the CAE codes in two-dimensional maps. To reduce the computational burden and overcome the out-of-sample projection diffusion in bi-kernel t-SNE, data subsampling is used in the training procedure. Finally, a one-class support vector machine is employed to calculate the visualization control boundary, and a batch-wise index is presented for fault wafer detection. To demonstrate the feasibility and effectiveness of the proposed method, it was applied to two wafer etching datasets. The results indicate that the proposed method outperforms state-of-the-art methods in data visualization and fault detection. [ABSTRACT FROM AUTHOR]

Spectroscopic ellipsometry is a very sensitive optical metrology technique commonly used in semiconductor manufacturing lines to accurately measure the thickness and refractive index of different layers present on specific dedicated metrology targets on the wafers. In parallel, optical defectivity techniques are widely implemented in production lines to inspect a significant amount of dies representative of the full wafer and detect physical and patterning defects. A new approach can then simply emerge which is to apply ellipsometry metrology techniques at a full or die wafer scale. This strategy, at the frontier between metrology and defectivity field is expected to bring solutions for certain types of process deviation. In our case, ellipsometry’s optical response was collected on large areas of product wafers to capture specific deviations such as film properties, thickness, and patterning variation. This is an innovative strategy that relies on a model-less approach to detect process drifts, using ellipsometry’s sensitivity to material properties and design architecture variations. In this paper, we will present this approach on three industrial cases. [ABSTRACT FROM AUTHOR]

Equipment at the end of functional life poses several challenges for manufacturing operations and long-term asset sustainability. This is even critical for semiconductor manufacturing where equipment upgrades are capital intensive with a longer return horizon. This demands an objective and quantifiable approach to manage and monitor the end-of-life health of the manufacturing systems. The paper presents a practical three-level approach that brings together engineering, operational, and supply chain factors under a single indicator. A visualization heatmap correlates equipment health to manufacturing impact for engineering and commercial decision-making. The approach is simple yet proven to be effective in fab environments. The proposed analysis applies in formulating system priorities, upgrade strategies, and capital expenditures. Brief guidance on health improvement strategies, application to new fab, and cost-based evaluation are presented for practical use. [ABSTRACT FROM AUTHOR]

The concepts of Industry 4.1 for achieving Zero-Defect (ZD) manufacturing were disclosed in IEEE Robotics and Automation Letters in January 2016. ZD of all the deliverables can be achieved by discarding the defective products via a real-time and online total inspection technology, such as Automatic Virtual Metrology (AVM). Further, the Key-variable Search Algorithm (KSA) of the Intelligent Yield Management (IYM) system developed by our research team can be utilized to find out the root causes of the defects for continuous improvement on those defective products. As such, nearly ZD of all products may be achieved. However, in a multistage manufacturing process (MMP) environment, a workpiece may randomly pass through one of the manufacturing devices with the same function in each stage. Different devices of the same type perform differently in each stage, where the performances will be accumulated through the designated manufacturing process and affect the final yield. KSA can only identify the influence of univariate variables (i.e., single devices) on the yield, yet it cannot detect the manufacturing paths that have significant influence on the yield. In order to cope with this deficiency such that the golden path with a better yield amongst all the MMP paths can be found, this research proposes the Golden Path Search Algorithm (GPSA), which can plan golden paths with high yield under the condition of the number of variables being much larger than that of samples. As a result, it makes the improvement of manufacturing yield be more comprehensive. Note to Practitioners—Traditional scheduling only considers the capacity of the manufacturing devices for allocation; while, the impact on the yield is rarely considered. In fact, in a production process, the production deviations will be gradually accumulated and affect the product quality along with the processing influence of each device. Therefore, the purpose of this paper is to propose the GPSA scheme to quickly search for high-yield manufacturing paths before the production. Manufacturers can then configure production devices based on these paths. According to the experimental results of real manufacturers’ data, GPSA can not only quickly nail down the high-yield paths from a large amount of historical data, but also alert the users to avoid paths that are prone to defective rates for their reference. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing processes, yield analysis aims to increase the yield by determining and managing the causes of low yield. The variable data collected from semiconductor manufacturing processes, in which hundreds of unit processes are implemented according to specific conditions and sequences, are interdependent, and the variables related to previous processes influence the variables in subsequent processes. Therefore, the order of processes should be considered when building a model that searches for the causes of low yield. However, there have been few studies in this area. This paper proposes a low-yield root cause search method considering the order of processes using a long short-term memory with attention mechanism (LSTM-AM) model. Specifically, the LSTM-AM model is applied to data classified according to the process structure of semiconductor products, and the causes of low yield are determined considering the order of processes by extracting attention weights. Experiments are conducted to verify the suitability of the proposed method using real yield data from a semiconductor company. The experimental results confirm that the proposed method outperforms the existing low yield root cause search methods in terms of low yield prediction. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing plays a crucial role in the world’s economic growth and technology development and is the backbone of the high value-added electronic device manufacturing industry. In this paper, a new anomaly detection framework by means of data visualization is proposed for semiconductor manufacturing. Firstly, t-Distributed Stochastic Neighbor Embedding (t-SNE) in unsupervised learning is used to transform the high-dimensional raw trace data, corresponding to normal wafers, into a two-dimensional map, with the purpose of visually observing the distribution of normal wafers. The t-SNE algorithm cannot be used at run time for a new test sample since it requires the whole dataset for the embedding transformation, and is computationally very expensive. The Multilayer Perceptron (MLP) neural network is then applied as a regressor for the real-time t-SNE embedding of a new test data. The envelope of t-SNE score estimates for a set of normal wafers is circumscribed and used as the 2D control boundary based on the Delaunay Triangulation (D.T.). A new test sample with its MLP estimated embedding points outside the D.T boundary is identified as defective. Lastly, a real-world dataset in semiconductor manufacturing is used to illustrate the proposed data visualization tool for anomaly detection. The experimental results show that a multilayer perceptron in combination with t-SNE and Delaunay Triangulation performs very well for data visualization and automated detection of anomalies. [ABSTRACT FROM AUTHOR]

Data-driven Fault Detection and Classification approaches are becoming increasingly important in semiconductor manufacturing and in other industries aiming at implementing the Zero-defect paradigm. Two of the main challenges in developing such solutions are: (i) the complexity of sensor data, that typically presents themselves in the form of time-series, requiring the employment of time-consuming and possibly sub-optimal feature extraction approaches; (ii) the fact that faults/defects may be caused by more than a single process, but in many cases they are generated by a cascade of processes. In this paper, we tackle the first issue, by considering a two-stage case study consisting of a deposition process and a rapid thermal process. The proposed approach is based on convolutional deep autoencoders employed to perform feature extraction from time-series sensor data in frontend production equipment. We will show on the reported case study, how the proposed approach outperfoms key numbers-based approaches typically used in the industry. To allow reproducibility of the reported results and to foster research in the field, we publicly share the data used in this work. [ABSTRACT FROM AUTHOR]

Semiconductors are essential components in many electronic devices. Because wafers are produced quickly and in large quantities, defects occur that adversely affect semiconductor properties. This makes it necessary to install powerful and robust inspection systems which use artificial intelligence techniques in the early stages of the manufacturing chain in order to detect and classify those defects. This paper proposes a method for defect detection and classification on images of semiconductor wafer materials obtained by means of a scanning electron microscope based in the following stages: (i) use of computer vision techniques to isolate the defect from the background; (ii) use of several descriptors based on shape, size, texture, histogram, and key-points to create a feature vector for the characterization of the defect; (iii) application of an exhaustive search as a feature selection method to determine the optimal subset of feature descriptors; and (iv) evaluation of the feature descriptors by using a support vector machine classifier providing the optimal set with highest F1-score metrics. Finally, the effectiveness of the proposed approach is compared with five popular feature selection methods, reporting better classification results than the latter. [ABSTRACT FROM AUTHOR]

Control of overlay errors in lithography process in semiconductor manufacturing uses in-process measurements of overlay errors from markers distributed across a wafer to adapt controllable process parameters on the relevant lithography tools in order to minimize future errors. Intuitively speaking, the use of a larger number of measurement markers should lead to improvements in one’s ability to control the overlay errors. However, those gains come with simultaneous increases in the metrology times, which negatively impacts throughput. Therefore, one should carefully and strategically select markers which most efficiently enable suppression of overlay errors. This paper proposes a novel optimization framework that couples a recently introduced approach for robust control of overlay errors in photolithography processes with a strategic selection of overlay measurement markers to enable improved control of overlay errors using a reduced number of measurements. Application of the newly proposed method to the data and models from an industrial-scale semiconductor lithography process shows that the newly proposed combination of the robust overlay control paradigm and optimized marker selection enables improved overlay control, even with a significantly reduced number of markers. Thus, the new methodology enables reduction of measurement times and subsequent overall cycle times, without deteriorating the outgoing product quality. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing is on the cusp of a revolution – the Internet of Things (IoT). With IoT we can connect all the equipment and feed information back to the factory so that quality issues can be detected. In this situation, more and more edge devices are used in wafer inspection equipment. This edge device must have the ability to quickly detect defects. Therefore, how to develop a high-efficiency architecture for automatic defect classification to be suitable for edge devices is the primary task. In this paper, we present a novel architecture that can perform defect classification in a more efficient way. The first function is self-proliferation, using a series of linear transformations to generate more feature maps at a cheaper cost. The second function is self-attention, capturing the long-range dependencies of feature map by the channel-wise and spatial-wise attention mechanism. We named this method as self-proliferation-and-attention neural network (SP&A-Net). This method has been successfully applied to various defect pattern classification tasks. Compared with other latest methods, SP&A-Net has higher accuracy and lower computation cost in many defect inspection tasks. [ABSTRACT FROM AUTHOR]

Wafer bin maps contain vital information that helps semiconductor manufacturers to identify the root causes and defect pattern failures in wafers. Conventional manual inspection techniques in inspecting these failures are labour intensive and cause prolonged production cycle time. Therefore, automatic inspection techniques can solve this problem. This paper proposes a deep learning approach based on deep convolutional generative adversarial network (DCGAN) and a new Capsule Network (WaferCaps). DCGAN was used to upsample the original dataset and therefore increase the data used for training and balance the classes at the same time. While WaferCaps was proposed to classify the defect patterns according to eight classes. The performance of our proposed DCGAN and WaferCaps was compared with different deep learning models such as the original Capsule Network (CapsNet), CNN, and MLP. In all of our experiment, WM-811K dataset was used for the data upsampling and training. The proposed approach has shown an effective performance in generating new synthetic data and classify them with training accuracy of 99.59%, validation accuracy of 97.53% and test accuracy of 91.4%. [ABSTRACT FROM AUTHOR]

Wafer fabrication (Wafer Fab) involves state-of-the-art, expensive, and highly complex processes, and only little is known about its change qualification, a process that follows a strict guideline to ensure that changes will affect neither the process flow nor the quality and reliability of the final saleable wafers. This paper proposes a five-stage change qualification framework in semiconductor manufacturing. We conceptualize our framework based on a stage-gate model and define suitable stages and gates for effective decision making. Afterward, we demonstrate its robustness via a case study, which provides an elaborate example that guided a requestor who successfully went through all stages of the change qualification process in reducing the occurrence of tool alarms. Our framework is proven to be complete and ready for deployment in the industry as a standard process flow in manufacturing technology management. [ABSTRACT FROM AUTHOR]

As we enter a New Year, we can look back on another year of solid accomplishment at IEEE Transactions on Semiconductor Manufacturing. I am happy to report that our impact factor remains steady at 2.70, and our mean time to first decision remains competitive at 8.3 weeks. Our Editorial Board remains as strong as ever, with the addition of Dr. Jun-Haeng Lee in the area of machine learning and data science applications in 2023, and we are actively seeking new board members. Our submissions remain strong, as do the special sections from conferences (ASMC, ISSM and CS-MANTECH). The Special Issue on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing appeared in the November issue, and two additional special issues are in preparation. Prof. Duane Boning of MIT and Dr. Bill Nehrer of Technology Consultancy are co-editing a special issue on “Semiconductor Design for Manufacturing,” which will be a collaborative effort with the IEEE Transactions on Electron Devices. Drs. Oliver Patterson of Intel and Tomasz Brozek of PDF Solutions are also co-editing a special issue on sustainable semiconductor manufacturing. We are also happy to announce the Best paper Award for 2023, in the companion editorial appearing in this issue. Congratulations to all the honorees, and we hope we will continue to see their submissions in the future. Our thanks go to Drs. Jeanne Bickford, Dragan Djurdjanovic and Mahadeva Iyer Natarajan for their work on this committee. [ABSTRACT FROM AUTHOR]

Searching for and comparing similar wafer maps can provide crucial information for root cause analysis in the manufacturing process of integrated circuits. Owing to the high dimensionality and complexity of defect patterns, comparison of similar maps in their entirety is inefficient. This paper proposes an automated similarity ranking system with a novel feature set as a reduced representation of wafer maps. To detect systematic failure patterns across wafer maps, we use nonparametric Bayesian clustering based on the Dirichlet process Gaussian mixture model, and hierarchical clustering based on the symmetric Kullback–Leibler divergence. The proposed features are efficient because they require minimal computation and storage; furthermore, they allow for highly discriminative rankings of similar failure patterns. Thus they are suitable for large-scale analysis of wafer maps. The proposed method is experimentally verified using a real wafer map dataset from a semiconductor manufacturing company, and a subset of WM-811K. [ABSTRACT FROM AUTHOR]

Detecting defects in the inspection stage of semiconductor manufacturing process is a crucial task to improve yield and productivity as well as wafer quality. Recent Advances in semiconductor process technology have greatly increased the transistor density. As a result, an increasingly high number of defects inevitably emerge and we need a more accurate and efficient detection method to manage them. In this paper, we propose a deep-learning-based defect detection model to expedite the process. It adopts an adversarial network architecture of conditional GAN. The discriminator of an adversarial network architecture helps the detection model learn to detect and classify defects accurately. The high performance is achieved by using Focal Loss, PixelGAN and multi-scale level features, which is shown to be better than the baseline model, CenterNet, when tested for a real industrial dataset. [ABSTRACT FROM AUTHOR]