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Among instances when the data and image security in resource constrained environment (smart devices and the like) are to be taken into consideration, lightweight encryption algorithms accede in popularity and are deemed of to be of great merit. In devices as those of the sort mentioned, reducing both power consumption and gate count is always a prime concern. LEA, therefore, triumphs on merit, owing to its low consumption levels of hardware resources, which itself is a result of the adaption of simple modular addition, bitwise rotation and bitwise XOR (ARX) operation instead of the relatively more complex S-box technique. The algorithm in question supports keys of varying sizes three, to be precise: 128, 192 and 256-bit for the intent of providing three levels of image and data security. The hardware implementation of the LEA algorithm for the varying key sizes as mentioned above share significant kinship and hardware resources. This paper puts forward the proposition regarding a high speed low area unified architecture for LEA algorithm for three different sizes of key. The individual hardware implementations of the three key sizes tend to consume more hardware resources than those involved in the proposed unified architecture. The pipelined implementation of the proposed design improves operating frequency to a significant degree, with a little increase in the hardware costs. The design proposed in this paper notably supports three varying tile sizes, i.e. 256 × 256 , 128 × 128 , 64 × 64, of an input image. As resolution of an input image may not necessarily be an integer multiple of the size of tile, smaller tile sizes at the image boundary can also be handled by the same architecture. The design hereby proposed has been implemented on both UMC ASIC 0.09- μ m and XC5VLX330T FPGA platforms and achieved maximum operating frequencies of 740 MHz and 292 MHz respectively. As its increasingly evident on account of the FPGA implementation outcomes, the proposed unified architecture results in vastly improved levels of operating frequency (34%, 33% and 131%) as opposed to the individually available LEA architectures (corresponding to three different key sizes: 128, 192 and 256-bit, respectively). Proposed architecture shows 28%, 35% and 45% increment in the hardware resources with respect to available LEA architectures with single key. The incorporation of the unified key generation technique and pipeline implementation of the algorithm are the main reasons for the more hardware utilization. [ABSTRACT FROM AUTHOR]