This paper describes implementation of the word boundary estimation module in FPGA. The boundary estimation module is based on energy detector. This module is optimized for implementation in FPGA. It occupies 54 logical elements "Slice" and uses only 0.7% of "Spartan-6 LX45" resources. Experiments with this module were performed at different signal/noise (S/N) ratio. For S/N of 20 dB and 15 dB word boundaries were estimated with 100% accuracy. Acceptable results were also achieved, for S/N ratio of 10 dB and 5 dB, as the estimation accuracy was 95% and 93%, respectively. [ABSTRACT FROM AUTHOR]
The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock. [ABSTRACT FROM AUTHOR]
*FIELD programmable gate arrays, *ALGORITHMS, *COMPUTER algorithms, *VHDL (Computer hardware description language), *STREAMING video & television
Abstract
The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84x84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640x480 pixel camera. [ABSTRACT FROM AUTHOR]