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This paper tackles a power minimization problem of interleave-division multiple-access (IDMA) systems over a fading multiple-access channel. The problem is minimizing the total power received by the receiver while keeping the bit error rates (BERs) of all users below a predefined value. The original formulation of the problem has highly nonlinear and implicitly defined functions, which render most existing optimization methods incapable. A new formulation is proposed in this paper, whose solution can effectively be obtained by a branch-and-bound (B&B) technique. An algorithm is devised based on B&B, and its effectiveness is also demonstrated by numerical experiments of systems with a moderate numbers of users. [ABSTRACT FROM AUTHOR]

This paper considers localization of a source or a sensor from distance measurements. We argue that linear algorithms proposed for this purpose are susceptible to poor noise performance. Instead given a set of sensors/anchors of known positions and measured distances of the source/sensor to be localized from them we propose a potentially nonconvex weighted cost function whose global minimum estimates the location of the source/sensor one seeks. The contribution of this paper is to provide nontrivial ellipsoidal and polytopic regions surrounding these sensors/anchors of known positions, such that if the object to be localized is in this region, localization occurs by globally exponentially convergent gradient descent in the noise free case. Exponential convergence in the noise free case represents practical convergence as it ensures graceful performance degradation in the presence of noise. These results guide the deployment of sensors/anchors so that small subsets can be made responsible for practical localization in geographical areas determined by our approach. [ABSTRACT FROM AUTHOR]

Waveform design is a pivotal component of the fully adaptive radar construct. In this paper, we consider waveform design for radar space time adaptive processing (STAP), accounting for the waveform dependence of the clutter correlation matrix. Due to this dependence, in general, the joint problem of receiver filter optimization and radar waveform design becomes an intractable, nonconvex optimization problem, Nevertheless, it is, however, shown to be individually convex either in the filter or in the waveform variables. We derive constrained versions of a) the alternating minimization algorithm, b) proximal alternating minimization, and c) the constant modulus alternating minimization, which, at each step, iteratively optimizes either the STAP filter or the waveform independently. A fast and slow time model permits waveform design in radar STAP, but the primary bottleneck is the computational complexity of the algorithms. [ABSTRACT FROM PUBLISHER]

This paper reports on enhancing the thermal performance of multiple-chip modules (MCMs) that contain a number of chips under natural convection by optimizing the chip placement layout. To attain this goal, an innovative hybrid optimization approach (HOA) incorporating a genetic algorithm (GA) into an algorithm based on a response surface method (RSM) is introduced for improving the performance of both these algorithms. The GA in the proposed HOA is responsible for not only evolving the population toward better fitness value but also, based on the newly evolved populations at each GA generation, for continuously updating the RS mathematical model for better approximation of the chip junction temperature. The sum of the mathematical expressions representing the total system temperature defines the objective of the optimization problems. For each GA generation, a constrained quadratic optimization subproblem is formed, based on the newly updated approximate RS mathematical model as the objective function along with the specified constraints. The solution of the optimization subproblem is sought through a mathematical programming model. As the genetic RS optimization progresses, a sequence of approximate solutions associated with the continuously updated RS mathematical models is constructed. The iterative process continues until convergence of the approximate solutions is attained. To demonstrate the effectiveness of the developed algorithm, several thermal design problems associated with two types of MCMs with equal/unequal power are performed. The obtained results are compared with those derived using two conventional approaches—the GA-based and the RSM-based optimization techniques. Results show that the developed algorithm can provide good optimal solutions with much less computational effort, and the larger the scale of the design problems, the more significant the improvement in the computation cost. [ABSTRACT FROM PUBLISHER]

Iterative shrinkage/thresholding (1ST) algorithms have been recently proposed to handle a class of convex unconstrained optimization problems arising in image restoration and other linear inverse problems. This class of problems results from combining a linear observation model with a nonquadratic regularizer (e.g., total variation or wavelet-based regularization). It happens that the convergence rate of these 1ST algorithms depends heavily on the linear observation operator, becoming very slow when this operator is ill-conditioned or ill-posed. In this paper, we introduce two-step 1ST (TwIST) algorithms, exhibiting much faster convergence rate than 1ST for ill-conditioned problems. For a vast class of nonquadratic convex regularizers (lP norms, some Besov norms, and total variation), we show that TwIST converges to a minimizer of the objective function, for a given range of values of its parameters. For noninvertible observation operators, we introduce a monotonic version of TwIST (MTwIST); although the convergence proof does not apply to this scenario, we give experimental evidence that MTwIST exhibits similar speed gains over 1ST. The effectiveness of the new methods are experimentally confirmed on problems of image deconvolution and of restoration with missing samples. [ABSTRACT FROM AUTHOR]

Consider directed acyclic graph (DAG) scheduling for a large heterogeneous system, which consists of processors with varying processing capabilities and network links with varying bandwidths. The search space of possible task schedules for this problem is immense. One possible approach for this optimization problem, which is NP-hard, is to start with the best task schedule found by a fast deterministic task scheduling algorithm and then iteratively attempt to improve the task schedule by employing a general random guided search method. However, such an approach can lead to extremely long search times, and the solutions found are sometimes not significantly better than those found by the original deterministic task scheduling algorithm. In this paper, we propose an alternative strategy, termed Push-Pull, which starts with the best task schedule found by a fast deterministic task scheduling algorithm and then iteratively attempts to improve the current best solution using a deterministic guided search method. Our simulation results show that given similar runtimes, the Push-Pull algorithm performs well, achieving results similar to or better than all of the other algorithms being compared. [ABSTRACT FROM AUTHOR]

To reduce field-programmable gate array power, Vdd programmability has been recently proposed to select the Vdd level for interconnects and power-gate unused interconnects. However, Vdd-level converters used in the existing Vdd-programmable method consume a large amount of leakage. This paper proposes two ways to avoid using level converters in interconnects, namely; 1) tree-based level converter insertion (TLC) and 2) dual-Vdd tree-based level converter insertion (dTLC). TLC enforces that there is only one Vdd level within each routing tree, while dTLC can have different Vdd levels within a routing tree, but no VddL switch drives VddH switches. Dual-Vdd assignment algorithms were developed considering chip-level time slack allocation for maximum power reduction. The algorithms include TLC-S and dTLC-S, two power sensitivity-based algorithms with implicit time slack allocation, and dTLC-LP, a linear programming (LP)-based algorithm with explicit time slack allocation. All allocate time slack first to interconnects with higher power sensitivity and assign low Vdd to them for more power reduction. Experiments show that dTLC-LP obtains the lowest power consumption. Compared to dTLC-LP, dTLC-S obtains a slightly higher power consumption but runs three times faster. Compared to the existing segment-based level converter insertion for dual Vdd, dTLC-LP reduces interconnect power by 52.90% without performance loss for Microelectronics Center of North Carolina benchmark circuits. [ABSTRACT FROM AUTHOR]

This paper presents a gate-sizing algorithm for coupling-noise reduction, which optimizes the area or power consumption (represented as a weighted sum of gate sizes) of a circuit while ensuring that its timing constraints are met. A problem for gate-size optimization under coupling-noise and timing constraints is formulated, and is broken down into two subproblems of gate-size optimization under noise and timing constraints, respectively. The subproblem of gate-size optimization under noise constraints is solved as a fixpoint computation problem on a complete lattice. The proposed algorithm to solve this problem is guaranteed to yield the optimal solution, provided it exists. The subproblem for circuit optimization under timing constraints is considered as a geometrical programming problem. The solutions to the two problems are finally combined to solve the original problem in a Lagrangian relaxation (LR) framework. Experimental results demonstrating the effectiveness of the algorithms are reported for the International Symposium on Circuits and Systems IISCAS) benchmarks and larger circuits. The obtained results are compared to the approach where successive iterations of gate sizing are performed for timing and for noise reduction independently. This alternative design approach is driven by the algorithms used to solving the mentioned subproblems, respectively. [ABSTRACT FROM AUTHOR]