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The article reports on the two technical papers presented at the recent International Interconnects Technology Conference in San Francisco, California. The papers indicated the semiconductor researchers' power-saving techniques as they scale chips to smaller sizes. Researchers from Intel Corp. showed direction on how to optimize repeater and logic transistor technologies, as well as improving repeater insertion methods and applying three-dimensional integration. Another paper from Georgia Institute of Technology suggested the use of carbon nanotubes to address some of the challenges of gigascale-integration interconnects.

Examines some of the process-specific papers in the 2003 Custom Integrated Circuits Conference in San Jose, California. Embedded software; Novel circuit architectures; Memory paradigms and packaging challenges.

Reports that the Custom Integrated Circuits Conference will be moved from May to September 21-24, 2003 at the Doubletree Hotel in San Jose, California. Benefit of the change to attenders and presenters; Deadline for the submission of papers for the event.