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This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

This paper proposes CMOS synapse and neuron for use in spiking neural networks to perform cognitive functions in a bio-inspired manner. The proposed synapse can trace the eligibility of the timing relationship between pre- and post-synaptic spikes, supporting a bio-plausible local learning rule called the spike timing-dependent plasticity (STDP) in an energy- and area-efficient manner. The proposed neuron can support neural functions such as synaptic current integration, threshold-based firing, neuronal leaking, membrane potential resetting, and adjustable refractory period with improved energy and area efficiency. The STDP curve shape of the synapse and the firing rate of the neuron can be adjusted as desired. Their variability due to process, voltage, and temperature (PVT) variations can also be minimized. The proposed CMOS neuron and synapse circuits were designed in a 28-nm CMOS process. The performance evaluation results indicate that the proposed synapse reduces energy consumption and area by up to 94% and 43% compared to conventional CMOS synapses. They also indicate that the proposed neuron achieves energy and area reductions of 37% and 23%, respectively, compared to conventional CMOS neurons. An associative neural network composed of the proposed neuron and synapse was designed to verify that they together work well for performing a cognitive function of associative learning and inferencing. [ABSTRACT FROM AUTHOR]

Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel-physics-based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of recurrent SNN using proposed low-power, low-area, and low-leakage band-to-band-tunneling (BTBT) based neurons. A low-power thresholding circuit is proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. The tunneling regime enables a high input impedance in the BTBT neurons (few $\text{G}\Omega$) to enable a voltage input without loading the synaptic array. To verify the effect of the proposed neuron, a 36-neuron recurrent SNN is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing. [ABSTRACT FROM AUTHOR]

In this paper, an analysis method is presented to mathematically characterize the harmonic current generated by the voltage at fundamental or harmonic frequency in the transistor of a high-frequency harmonic oscillator. Using this analysis method, the relationship between the second harmonic voltages and the fourth harmonic drain current in the transistor is investigated, and the requirement on the second harmonic voltages for fourth harmonic boosting is found. Moreover, an approach of modeling the voltage-current relationship in the transistor of a high-frequency harmonic oscillator at harmonic frequency as an equivalent linear relationship is proposed. This modeling method facilitates the design of the second harmonic embedding network around the transistor, thus helping to propose a harmonic oscillator topology in which the requirement on the second harmonic voltages for fourth harmonic boosting is fulfilled. Using the proposed fourth harmonic boosting technique, a 0.6-THz radiator array is designed in 40-nm bulk CMOS. In measurement, the 0.68- $\text {mm}^{2}$ radiator array achieves a radiated power of 0 dBm and a DC-to-THz efficiency of 0.08% at 586.7 GHz under a 0.9-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%. [ABSTRACT FROM AUTHOR]

This paper presents a 46 nF/10 $\text{M}\Omega $ -range, digital-intensive, reconfigurable RC-to-digital converter (R2CDC) that can readout multiple C and R sensors in a time-interleaved fashion. Ratio-metric conversion using swing-boosted period-modulation (SB-PM) front-end by the R2CDC results in 114 aFrms/ $0.37 \Omega _{\text {rms}}$ resolutions and a worst-case temperature-drift of 64.2 ppm/°C over −40 to 125°C. Femto-farad capacitances can be sensed with a relative code-deviation less than 0.16 % even when parasitics vary 30 times the baseline. Implemented in a $0.18 ~\mu \text{m}$ standard CMOS process, the R2CDC consumes 140 $\mu \text{A}$ from a 1 V supply, occupying an active area of $0.175 ~\mu \text{m} ^{\mathrm{ 2}}$. [ABSTRACT FROM AUTHOR]

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies. [ABSTRACT FROM AUTHOR]

In this paper, the design of a 77.3 GHz Standing-Wave oscillator (SWO) is presented. The proposed SWO relies on the distribution of varactors along an asymmetrical slow-wave coplanar stripline, which enables the improvement of the quality factor of the tunable resonator, resulting in superior performance in terms of phase noise and DC-to-RF efficiency. The design methodology, based on the use of analytical models and abaci, is presented in detail and applied to a design in a 55-nm CMOS technology. With a core consumption of 15.1 mW, the proposed SWO operates from 76.09 GHz to 78.60 GHz and presents a phase noise of −115.1 dBc/Hz at 10 MHz offset, leading to a Figure of Merit (FOM) of −181 dBc/Hz. The DC-to-RF efficiency obtained is 3.1%. [ABSTRACT FROM AUTHOR]

This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5 $\text{m}\text {V}_{\text {pp}}$ differential input ($\Delta V_{\textrm {I}}$) at 0.5 V common-mode ($V_{\textrm {CM}}$) and 1V supply ($V_{\textrm {DD}}$). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a < 70ps delay down to 0.6 V $V_{\textrm {DD}}$. The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution. [ABSTRACT FROM AUTHOR]

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ($\mathrm {P}_{\mathrm {DC}}$), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs $\ge80$ GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ($\mathrm {P}_{\mathrm {DC}}$) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per $\mathrm {P}_{\mathrm {DC}}$ (${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$) of 6.01 GHz/mW while being power-efficient. [ABSTRACT FROM AUTHOR]

Being an indispensable technique in the standard laboratory, Nuclear Magnetic Resonance (NMR) is a versatile method to non-invasively observe the atomic and molecular information of the samples containing non-zero spin nuclei. Yet, the bulky and costly hardware for NMR impedes their broad distributions outside the laboratory for on-demand and on-line usage. In recent years, with the advance in microelectronics, NMR systems equipped with customized silicon chips emerged to achieve system miniaturization with performance enhancement, and pioneer novel applications that were not feasible before using discrete NMR electronics. This article overviews the hardware for NMR from the system-level perspective, and examines the latest developments using integrated circuits over the past decade. Also, we present in detail the design considerations of the transmitter and receiver that are the cornerstone of micro-NMR systems. [ABSTRACT FROM AUTHOR]

A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based $4^{\mathbf {th}}$ -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ($\text{S}_{{21}}$) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of $>\!\!\!-12.8$ dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows $\text{S}_{{21}}$ of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm2. The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively. [ABSTRACT FROM AUTHOR]

This article revisits the concept of “noise measure” and its importance in designing high-frequency low-noise amplifiers. A new derivation is offered which is simpler than the original derivation of Haus and Adler. Several examples are used to calculate the minimum noise measure of a CMOS amplifier. It is also shown that “noise cancellation” techniques cannot improve the minimum noise measure. [ABSTRACT FROM AUTHOR]

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N $f_{0}$) while canceling the fundamental ($f_{0}$) and the 2nd to (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential $\times 6$ frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented $\times 6$ frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2nd to 5th harmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit. [ABSTRACT FROM AUTHOR]

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves >5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency. [ABSTRACT FROM AUTHOR]

This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a $0.25~\mu \text{m}$ CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/ $\mu \text{s}$ at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm2. The GI system exhibits robust performance to fabrication variations, with less than ±0.3% and ±8% sensitivity to process variation and post-assembly chip distance offset, respectively. [ABSTRACT FROM AUTHOR]

In this work, we report the portable NMR system which provides solutions to the existing problems in miniature CMOS NMR systems. First, a higher IF of 50 kHz is achieved by exploiting separate frequencies for sample excitation and LO, thereby having higher immunity to 1/f noise. The proposed phase detector circuit aligns the experiment trigger with the constant phase difference between two frequencies. It maintains the constant RX output phase in every experiment, allowing the direct signal averaging without extra phase correction. In addition, 40X faster RX recovery with RX BW switching enables the signal acquisition with the dead time of 10 $\mu \text{s}$. Fast settling improves the acquisition sensitivity. Lastly, a frequency calibration method based on signal peak detection is proposed. Combining the techniques with the fully integrated NMR transceivers, the system demonstrates the NMR experiments to measure the decaying time constant of less than 100 $\mu \text{s}$. Furthermore, NMR diffusion experiments are performed with the echo spacing of $0.2\sim 8$ ms. [ABSTRACT FROM AUTHOR]

Charge balancing has become a common key safety requirement of electrical stimulation systems. It reduces the risk of electrode dissolution and tissue damage, which might arise after unbalanced stimulation pulses. A CMOS integrated consequence-based active charge balancer is presented that instantaneously removes excess charges between two consecutive stimulation pulses. This balancer provides a highly adaptive power supply compliance from 3.3 V to 38 V, verified by measurements. In order to maintain the compensation behavior and efficacy over the entire supply range and to protect the active components at such high voltages, a quad-rail design is elaborated that overcomes the technological high voltage limitations of the employed 0.35 $\mu \text{m}$ CMOS process. The presented charge balancing circuit consists of a fully differential operational transconductance amplifier for monitoring and voltage level translation, as well as an advanced class-B stage as current driver, designed in accordance with the quad-rail concept. Further system flexibility is provided by incorporating three different compensation current limitations of $\pm 500~\mu \text{A}$ , $\pm 300~\mu \text{A}$ and $\pm 200~\mu \text{A}$. Additionally, two safety limits of ±50 mV and ±100 mV have been adopted. The charge balancer is very power efficient, it only dissipates 6.3 $\mu \text{W}$ and 25 $\mu \text{W}$ , at 3.3 V and 38 V respectively. [ABSTRACT FROM AUTHOR]