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In this paper, we propose a method for calculating the DC source amplitude in an extended multilevel inverter (MLI) structure so that the maximum number of levels and the output voltage waveform are as close as possible to the sinusoidal wave with minimum total harmonic distortion (THD). For the developed structure, three algorithms are suggested to determine the amounts of DC voltage resources. The first important point about choosing the right amounts for the DC resources is that the number of levels should be as large as possible, and the second important point is that the intervals between the levels should be the same throughout the waveform. By observing these two points, the output voltage waveform can be as near as possible to the sinusoidal wave that we want. In this study, we used iteration-based methods to find suitable values for DC sources. Simulation results are offered to confirm the capability of the extended multilevel converter. After we solved the problem through calculation and analysis, a code was written in MATLAB with the aim that this time the code will tell us for what values of DC sources we will have the largest number of levels and as we expected, the output of the MATLAB code confirmed the correctness of the calculations. [ABSTRACT FROM AUTHOR]

As a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively. [ABSTRACT FROM AUTHOR]