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This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

A circuit-oriented geometrical approach in predicting subharmonic oscillation (SHO) of voltage-mode switching converters is presented. It is based on a straightforward graphical analysis of the operation of the converter without using advanced mathematical techniques. It is shown that the slope of the output of the compensator at the trip point is an important factor in determining the onset of SHO. The critical condition of SHO of the buck converter working in continuous conduction mode (CCM) is derived and expressed in terms of circuit parameters that serve as the design guideline for avoiding SHO. The proposed approach is applied to analyze three schemes, namely, proportional, dominant-pole and Type-III compensation. The analysis of SHO in discontinuous conduction mode (DCM) for both the buck and the boost converters are also included to demonstrate the universality of the proposed approach. Crucial Cadence simulation results and measurement results are presented to verify the analysis. [ABSTRACT FROM AUTHOR]