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Summary: A high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2. [ABSTRACT FROM AUTHOR]

—In this paper, a class-F 23 VCO using nonlinear-capacitance transforming technique to simultaneously achieve low phase noise and a wide tuning range is proposed. The phase noise degradation due to the nonlinearity of the switched capacitor in the class-F 23 oscillator is analyzed and quantitatively derived. The phase noise contributed by the nonlinear capacitance can be suppressed by using the proposed nonlinear-capacitance transformation technique. In order to achieve low phase noise over a wide bandwidth, the asymmetric-toggling method is utilized to achieve optimal capacitance ratios across the entire frequency range. Implemented in a 40-nm CMOS process, the proposed oscillator exhibits 41.2 % tuning range from 2.58 GHz to 3.92 GHz while consuming 13.8 mW–14.9 mW power dissipation. The phase noises at 2.58 GHz and 3.92 GHz oscillation frequencies are −136.4 dBc/Hz and −129.6 dBc/Hz at 1-MHz offset. The minimum phase noise is −157.2 dBc/Hz at 10 MHz offset, corresponding to an FoM of 194.1 dBc/Hz and FoM T of 206.4 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper presents an accurate ISF-based phase noise analysis method for LC/Ring oscillators. The proposed method can simultaneously quantify the effect of flicker noise and thermal noise on phase noise. The impulse sensitivity function (ISF) tool is used to evaluate the effect of flicker noise sources. An equivalent thermal noise resistor is utilized to assess the thermal noise contribution and simplify the analysis process. Based on the proposed method, the phase noise performance of a voltage-controlled oscillator (VCO) with source damping resistors is discussed. Simulated in 180-nm TSMC and 110-nm HHGRACE CMOS processes, the accuracy of the proposed method is verified. The predicted phase noise performance is consistent with the simulation results in 1/ f 3 and 1/ f 2 region, achieving 1-dB accuracy in diverse oscillator topologies. [ABSTRACT FROM AUTHOR]