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The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84x84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640x480 pixel camera. [ABSTRACT FROM AUTHOR]

Turbo code is one of the most significant achievements in coding theory during the last decade. By concatenating two simple convolutional codes in parallel, it has been shown that transmission systems employing turbo codes could offer near-capacity performance. More importantly, by employing a suboptimal iterative decoding structure with soft-in/soft-out (SISO) maximum a posteriori-probability (APP) decoding algorithm, the near-capacity performance is achievable at a feasible decoding complexity. Given the outstanding performance of turbo code, the challenge now is to implement it into various communication systems at affordable decoding complexity using current very large scale integration (VLSI) technologies. In this paper, we first investigated the existing four different turbo decoding algorithms. Comparisons of both their performances and implementation complexities were performed. Log-maximum a posteriori (MAP) -based turbo decoding was found to offer the best performance-complexity compromise. A register-transfer-level (RTL) 12-bit fixed-point turbo decoder based on Log-MAP algorithm was then designed and simulated using VHDL as the hardware description language. The implemented RTL model was verified by comparing its performances with those obtained from a C-language implementation of the same turbo decoder. [ABSTRACT FROM AUTHOR]

A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data portion can only be modeled by extended finite-state machines (EFSMs). However, infeasible paths due to the conflicts among the condition and action variables of EFSMs complicate the test generation process. This paper introduces a method enabling the automatic generation of realizable test sequences from a class of EFSMs. Algorithms to detect and eliminate conflicts caused by the interdependencies among the variables of a class of EFSM models are presented. After all conflicts are eliminated from the EFSM graph, the existing FSM-based automated test generation methods can be used to generate feasible test sequences. Recently, these algorithms have been implemented as a software package called INDEEL. This methodology is applied to generate feasible tests for protocols such as ACA and MIL-STD 188-220. Current applications include IETF protocols and ASAP. [ABSTRACT FROM AUTHOR]