Search

Abstract: Radio-frequency identification (RFID) is a recent technology that utilizes radio frequencies to track the object by transmitting a signal with a unique serial identity. Generally, the drawbacks of RFID technology are high cost and authentication systems between a reader and a tag become weak. In this paper, we proposed a protocol for RFID tag–reader mutual authentication scheme which is hardware efficient and consumes less dynamic power. Truncated multipliers are implemented in RFID tag–reader mutual authentication protocol system due to reduction in hardware cost and dynamic power. Experimental evaluation reveals that the proposed protocol with truncated multipliers provides more security than the earlier schemes. The proposed protocol is described in VHDL and simulated using Altera Quartus II. The functional block is implemented as hardware using an Altera DE2 Cyclone II (EP2C35F672C6) Field-Programmable Gate Array (FPGA). [Copyright &y& Elsevier]

The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84x84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640x480 pixel camera. [ABSTRACT FROM AUTHOR]