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NoC technology is composed of packet-based interconnections, where the communication resources are distributed across the network. Therefore, the optimal resource utilization is a crucial consideration for efficient architectural designs. This paper studies the practicality of the Constraint Programming (CP) models for NoC architecture designs that effectively use a regular mesh with wormhole switching and the XY routing. The complexity of the CP models is compared with the earlier Mixed Integer Programming (MIP) models. Practical CP-based mapping and scheduling models are developed and results are reported on the benchmark datasets. Results indicate that mapping and scheduling problems can be solved at near optimality even under relatively shorter run-time limits as compared to those required by the MIP models. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstraction. Experimental results show that our power macro model incurs less than 5% average absolute cycle error compared to gate level analysis. The high level power macro model allows network power to be readily incorporated into simulation infrastructures, providing a fast and cycle accurate power profile, to enable power optimization such as power-aware compiler, core mapping, and scheduling techniques for CMP. As a case study, we demonstrate the use of our model for evaluating the effect of different core mappings using SPLASH-2 benchmark showing the utility of our power macro model. [Copyright &y& Elsevier]

Abstract: Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is desirable to consider interconnection network''s power efficiency when designing CMP. In this paper, we present a variable frequency link for a power-aware interconnection network using the clock boosting mechanism, and apply a dynamic frequency scaling (DFS) policy, that judiciously adjusts link frequency based on link utilization parameter. Experimental result shows that history-based DFS successfully adjusts link frequency to track actual link utilization over time, demonstrating the feasibility of the proposed link as a power-aware interconnection network for system-on-chip (SoC). [Copyright &y& Elsevier]

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long-distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock-free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture. [ABSTRACT FROM AUTHOR]

Cache coherence plays a major role in manycore systems. The verification of deadlocks is a challenge in particular, because deadlock freedom is an emerging property. Formal methods often decouple verification of the protocol from verification of the communication interconnect. Modern communication fabrics, however, become more advanced and include a network topology, routing, arbitration, synchronization, and more. In this paper, an integrated approach is proposed that allows cross-layer verification of both the cache coherence protocol and the communication fabric all at once. An automated methodology for deriving cross-layer invariants is proposed. These invariants relate the state of the application-layer protocols to en route packets in the communication fabric. Using the invariants, we derive formal proofs of deadlock-freedom for two case studies: a directory-based MI protocol in a 2D mesh, and a ring-based snoopy protocol in a 2D torus. Additionally, we show that our methodology can be used to derive the smallest possible queue sizes that ensure absence of deadlocks. Our methodology is generally applicable and shows promising scalability. [ABSTRACT FROM PUBLISHER]

Abstract: This paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked mesh NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power consumption requirements. The proposed architecture uses an adaptive quasi-minimal routing algorithm so that it can improve average latency and saturation traffic load owing to its flexibility and adaptiveness. Based on these features, a congestion-aware routing algorithm is proposed to balance traffic load so as to alleviate congestion caused by high throughput network activities. Simulation results show that saturation load is improved dramatically for various traffic patterns. Implementation results also show that employing diagonal links is a more area-efficient method for improving network performance than using large buffers. It is shown that congestion-aware router requires negligible cost overhead but provides better throughput. Finally, simulation results also reveal that power consumption in the proposed architecture outperforms traditional mesh networks. [Copyright &y& Elsevier]