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Convolutional neural networks have been proposed as an approach for classifying data corresponding to a variety of datasets. Indeed, developments in data diversity and information technology have increased the complexity of deep learning algorithms. Numerous trained models have been proposed for supporting complex algorithms and data detachment with high accuracy. Convolutional operations increase when the convolution depth of neural networks increases. Thus, employing deep convolutional networks is challenging regarding energy consumption, bandwidth, memory requirements, and memory access. Different types of on-chip communication platforms and traffic distribution methods are effective in the improvement of memory access and energy consumption induced by data transfer. Also, dataflow mapping methods have an impressive effect on reducing or increasing delay and energy consumption caused by exchanging data between cores of a communication network. Different methods have been proposed to dataflow mapping on various networks for reducing total hop counts that led to improve performance and cost. Dataflow mapping approach can affect performance improvement of the inference phase in neural networks. This paper proposes various traffic patterns by considering different memory access mechanisms for traffic distribution of a trained AlexNet model on mesh topology. We propose a flow mapping method (FMM) on the mesh to determine the data flow efficiency of different traffic patterns on energy consumption. The FMM reduced energy and total flow by approximately 17.86% and 34.16%, respectively, using different traffic patterns. Thus, the FMM improved the performance of AlexNet traffic distribution while the impact on data flow reduced energy consumption. [ABSTRACT FROM AUTHOR]

Abstract: Adaptive routing algorithms have been employed in interconnection networks to improve network throughput and provide better fault tolerance characteristics. However, they can harm performance by disturbing any inherent global load balance through greedy local decisions. This paper proposes a novel scalable load balancing congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also improves overall network throughput for various traffic scenarios. This congestion control scheme which consists of dynamic input arbitration and adaptive routing path selection is proposed to balance global traffic load distribution so as to alleviate congestion caused by heavy network activities. Furthermore, faulty links information can be broadcasted by existing congestion management control signals to prevent packets from routing through defected areas in order to eliminate potential heavy congestion situations around these regions. Experimental results show that throughput is improved dramatically while maintaining superior latency performance for various traffic patterns. Compared to a baseline router, the proposed congestion management mechanism requires negligible cost overhead but provides better throughput for both mesh and diagonally-linked mesh NoC platforms. [Copyright &y& Elsevier]