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This paper presents two new ternary operators which can be used in different scrambling crypto algorithms. The employment of the proposed operators ( ScramOp1 and ScramOp2 ) leads to reduction in the number of decoding steps, equivalent to only one operation per digit for the receiver side. These operators are presented for the first time in ternary logic. There are some other ternary operators such as SUM , which are specifically suitable for computer arithmetic but they lack desirable efficiency for cryptographic applications. The transistor-level designs of the operators are simulated by using Synopsys HSPICE with 32 nm bulk-CMOS technology. Simulation results demonstrate that ScramOp1 and ScramOp2 achieve significant saving in energy consumption (2.11% and 12.14%) in comparison with SUM . Additionally, ScramOp2 requires only 52 transistors while 58 and 60 transistors are needed to implement ScramOp1 and SUM , respectively. [ABSTRACT FROM AUTHOR]

Nanotechnologies, notably quantum-dot cellular automata, have achieved world-wide attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, energy consumption and latency of circuits, is considered as a potential alternative for the CMOS technology. Considering the manufacturing aspects, in this paper, a method is proposed for designing efficient quantum-dot cellular automata circuits. We inspect an alternative approach for streamlined design of quantum-dot cellular automata circuits such that the required external fixed inputs are substantially reduced. In order to demonstrate the efficiency of the proposed method, the widely used multiplexer, XOR and party generator circuits are considered as case studies. All of the proposed circuits are simulated and verified using QCADesigner which is a valid and popular simulation tool. Comparisons indicate that the proposed method considerably reduces the number of external fixed inputs which simplifies the overall circuit implementation and fabrication. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. In this study a low complexity and energy-efficient QCA T flip–flip as well as high-performance single-layer synchronous counters are proposed. By cascading the proposed T flip-flop and a suitable level converter, a QCA-compatible structure for falling edge triggered T flip-flop is achieved. This circuit functions as the chief element for constructing synchronous counters. QCADesigner and QCAPro tools are used for evaluating the functionality and calculating dissipated energy of the circuits, respectively. Results indicate the superiority of the proposed circuits in terms of complexity, latency and energy consumption as compared to their state-of-the-art counterparts. The proposed T flip-flop demonstrates 18% leakage energy improvement besides the considerable value of 56% switching energy improvement in 0.5Ek tunneling energy level as compared to the best ones. It is worth mentioning that 41%, 44% and 45% optimizations in the number of cells in addition to 15%, 25% and 33% optimizations in the area are achieved for the proposed mod 4, mod 8 and mod 16 counters, respectively, in comparison with the best previous results. [ABSTRACT FROM AUTHOR]