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A high reliability offset-tolerant sensing circuit is presented for deep submicron spin transfer torque magnetic tunnel junction (STT-MTJ) memory. This circuit, using a triple-stage sensing operation, is able to tolerate the increased process variations as technology scales down to the deep submicron nodes, thus improving significantly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance during the sensing operations. By using the STMicroelectronics CMOS 40 nm design kit and a precise STT-MTJ compact model, Monte Carlo simulations have been carried out to evaluate its sensing performance. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues. [ABSTRACT FROM AUTHOR]

We review the recent progress in the development of magnetoelectric RAM (MeRAM) based on electric-field-controlled writing in magnetic tunnel junctions (MTJs). MeRAM uses the tunneling magnetoresistance effect for readout in a two-terminal memory element, similar to other types of magnetic RAM. However, the writing of information is performed by voltage control of magnetic anisotropy (VCMA) at the interface of an MgO tunnel barrier and the CoFeB-based free layer, as opposed to current-controlled (e.g., spin-transfer torque or spin-orbit torque) mechanisms. We present results on voltage-induced switching of MTJs in both resonant (precessional) and thermally activated regimes, which demonstrate fast (<1 ns) and ultralow-power (<40 fJ/bit) write operations at voltages \sim 1.5-2~V . We also discuss the implications of the VCMA-based write mechanism on memory array design, highlighting the possibility of crossbar implementation for high bit density. Results are presented from a 1 kbit MeRAM test array. Endurance and voltage scaling data are presented. The scaling behavior is analyzed, and material-level requirements are discussed for the translation of MeRAM into mainstream memory applications. [ABSTRACT FROM AUTHOR]

We studied the spin transfer torque (STT) driven switching voltage distribution systematically by characterizing the switching probability density function (PDF) with large statistics (10^5 trials) across a wide time scale from 5 ns to 1 \mus. The skew normal distribution function is found to be a good one to fit the measured switching PDF down to low values, which would be used as a guideline to extrapolate read disturb rate (RDR) and write error rate (WER) in STT-RAM design. Moreover, the asymmetry of switching probability density function is observed to flip when the pulse width decreases. It is related to the fluctuation mechanism transition from the thermal agitation to the initial magnetization trajectory dispersion. [ABSTRACT FROM AUTHOR]