1. A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator.
- Author
-
Shu, Yiyang, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
- *
PHASE noise , *QUADRATURE domains , *VOLTAGE , *PHASE-locked loops , *FREQUENCY synthesizers - Abstract
A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are −188.2 dBc/Hz and −200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from −104.1 to −108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is −236.2 dB. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF