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Measurements of the near-interface oxide traps (NIOTs) aligned to the conduction band of silicon-carbide (SiC) are of particular importance as these active defects are responsible for degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this brief, a new method for measurement of the active NIOTs with energy levels aligned to the conduction band is proposed. The method utilizes transient-current measurements on 4H-SiC MOS capacitors biased in accumulation. Nitrided oxide and dry oxide are used to illustrate the applicability of the proposed measurement method. [ABSTRACT FROM AUTHOR]

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect. [ABSTRACT FROM AUTHOR]

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region. [ABSTRACT FROM AUTHOR]

This paper reviews the feasibility of the state-of-the-art electrical techniques adopted from Si technology for characterization of SiC MOS devices. The inability of these conventional characterization techniques to correctly evaluate the trap capture cross section and field-effect mobility in SiC MOS devices are investigated and explained. As near-interface traps (NITs) are an important cause of field-effect mobility degradation in SiC MOS devices, which is different from the impact of interface traps in Si devices, these characterization techniques are unable to produce meaningful results. Therefore, special care is required when measuring these NITs in SiC MOS devices. Due to the quantum confinement effect, the NITs located above the conduction band edge are able to capture and release channel electrons from the conduction band via tunnelling. Recent characterization techniques, specifically designed for SiC MOS devices, measure the NITs above the bottom of conduction band and consider the quantum confinement effect to find the energy position of the NITs. These recent characterization techniques are presented in the later part of the paper. [ABSTRACT FROM AUTHOR]

• In this paper we have implemented a recently proposed direct-measurement technique to characterize near-interface traps (NITs) in SiC MOS capacitors with gate oxides obtained by four different processes. • This measurement technique enables characterization of NITs with energy levels above the bottom of the conduction band, which are active in the accumulation mode of MOS capacitors on N-type SiC and in the strong inversion of N-channel MOSFETs. • The measurements revealed that annealing in nitric oxide of thermally grown oxides in dry oxygen removes NITs that are further away from the SiC surface, but it leaves a defect with energy levels located between 0.13 eV and 0.23 eV above the bottom of conduction band. • The oxides grown in pure nitric oxide exhibit NITs with energy levels above 0.2 eV. • The measurements also show that low-temperature oxide deposition and subsequent annealing in nitric oxide resulted in the lowest density of NITs. In this paper we have implemented a recently proposed direct-measurement technique to characterize near-interface oxide traps (NITs) in SiC MOS capacitors with gate oxides obtained by four different processes. This measurement technique enables characterization of NITs with energy levels above the bottom of the conduction band, which are active in the accumulation mode of MOS capacitors on N-type SiC and in the strong inversion of N-channel MOSFETs. The measurements revealed that annealing in nitric oxide of thermally grown oxides in dry oxygen removes NITs that are further away from the SiC surface, but it leaves a defect with energy levels located between 0.13 eV and 0.23 eV above the bottom of conduction band. The oxides grown in pure nitric oxide exhibit NITs with energy levels above 0.2 eV. The measurements also show that low-temperature oxide deposition and subsequent annealing in nitric oxide resulted in the lowest density of NITs. [ABSTRACT FROM AUTHOR]