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Abstract: Congestion estimation plays an important role in the physical layout of VLSI design. This paper presents a new probabilistic estimation model that improves the previous estimators by relaxing the constraint on detours in a route. The model is more general and realistic for it gives the flexibility for the wires to have wider usage area to bypass the congestion regions and blockages. Given a routing grid and a set of nets to be routed, the model predicts the routing density on each edge of the grid. The routing density provides direct congestion estimation. We compare our estimation results to the actual routing results. Experimental results show the effectiveness of our estimator. [Copyright &y& Elsevier]

Interconnect planning is an important issue in VLSI designs. Routing congestion is an important problem during placement. This paper presents a novel approach to estimating the routing congestion on the hexagonal model with bounded-length detours. It is the first probabilistic estimation work on hexagonal topologies. A combinatorial estimation algorithm is presented. The experimental results demonstrate the effectiveness of the method. [ABSTRACT FROM AUTHOR]