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The field of bioelectronics with the aim to contact cells, cell clusters, biological tissues and organoids has become a vast enterprise. Currently, it is mainly relying on classical micro‐ and nanofabrication methods to build devices and systems. Very recently the field is highly pushed by the development of novel printable organic, inorganic and biomaterials as well as advanced digital printing technologies such as laser and inkjet printing employed in this endeavor. Recent advantages in alternative additive manufacturing and 3D printing methods enable interesting new routes, in particular for applications requiring the incorporation of delicate biomaterials or creation of 3D scaffold structures that show a high potential for bioelectronics and building of hybrid bio‐/inorganic devices. Here the current state of printed 2D and 3D electronic structures and related lithography techniques for the interfacing of electronic devices with biological systems are reviewed. The focus lies on in vitro applications for interfacing single cell, cell clusters, and organoids. Challenges and future prospects are discussed for all‐printed hybrid bio/electronic systems targeting biomedical research, diagnostics, and health monitoring. [ABSTRACT FROM AUTHOR]

Printed electronics including large‐area sensing, wearables, and bioelectronic systems are often limited to simple circuits and hence it remains a major challenge to efficiently store data and perform computational tasks. Memristors can be considered as ideal candidates for both purposes. Herein, an inkjet‐printed memristor is demonstrated, which can serve as a digital information storage device, or as an artificial synapse for neuromorphic circuits. This is achieved by suitable manipulation of the ion species in the active layer of the device. For digital‐type memristor operation resistive switching is dominated by cation movement after an initial electroforming step. It allows the device to be utilized as non‐volatile digital memristor, which offers high endurance over 12 672 switching cycles and high uniformity at low operating voltages. To use the device as an electroforming‐free, interface‐based, analog‐type memristor, anion migration is exploited which leads to volatile resistive switching. An important figure of merits such as short‐term plasticity with close to biological synapse timescales is demonstrated, for facilitation (10–177 ms), augmentation (10s), and potentiation (35 s). Furthermore, the device is thoroughly studied regarding its metaplasticity for memory formation. Last but not least, the inkjet‐printed artificial synapse shows non‐linear signal integration and low‐frequency filtering capabilities, which renders it a good candidate for neuromorphic computing architectures, such as reservoir computing. [ABSTRACT FROM AUTHOR]

The high‐entropy approach is applied to monoclinic Prussian White (PW) Na‐ion cathodes to address the issue of unfavorable multilevel phase transitions upon electrochemical cycling, leading to poor stability and capacity decay. A series of Mn‐based samples with up to six metal species sharing the N‐coordinated positions was synthesized. The material of composition Na1.65Mn0.4Fe0.12Ni0.12Cu0.12Co0.12Cd0.12[Fe(CN)6]0.92□0.08 ⋅ 1.09H2O was found to exhibit superior cyclability over medium/low‐entropy and conventional single‐metal PWs. We also report, to our knowledge for the first time, that a high‐symmetry crystal structure may be advantageous for high‐entropy PWs during battery operation. Computational comparisons of the formation enthalpy demonstrate that the compositionally less complex materials are prone to phase transitions, which negatively affect cycling performance. Based on data from complementary characterization techniques, an intrinsic mechanism for the stability improvement of the disordered PW structure upon Na+ insertion/extraction is proposed, namely the dual effect of suppression of phase transitions and mitigation of gas evolution. [ABSTRACT FROM AUTHOR]

The high‐entropy approach is applied to monoclinic Prussian White (PW) Na‐ion cathodes to address the issue of unfavorable multilevel phase transitions upon electrochemical cycling, leading to poor stability and capacity decay. A series of Mn‐based samples with up to six metal species sharing the N‐coordinated positions was synthesized. The material of composition Na1.65Mn0.4Fe0.12Ni0.12Cu0.12Co0.12Cd0.12[Fe(CN)6]0.92□0.08 ⋅ 1.09H2O was found to exhibit superior cyclability over medium/low‐entropy and conventional single‐metal PWs. We also report, to our knowledge for the first time, that a high‐symmetry crystal structure may be advantageous for high‐entropy PWs during battery operation. Computational comparisons of the formation enthalpy demonstrate that the compositionally less complex materials are prone to phase transitions, which negatively affect cycling performance. Based on data from complementary characterization techniques, an intrinsic mechanism for the stability improvement of the disordered PW structure upon Na+ insertion/extraction is proposed, namely the dual effect of suppression of phase transitions and mitigation of gas evolution. [ABSTRACT FROM AUTHOR]

In solution processed electronic devices it is crucial that the deposited inks are properly aligned and that all post‐processing steps are compliant with each other. Moreover, shorter channel lengths are highly beneficial to increase the device performance. Herein, laser printing of metals and polymer reservoirs allows to print sub‐micrometer sized channel lengths while confining functional inks into these small gaps. Therefore, a manufacturing concept and optimized material stack, suitable for combined inkjet and laser printing are proposed. A nanoparticulate indium oxide (In2O3) semiconductor is inkjet printed into and constrained by a 3D laser written polymer (pentaerythritol triacrylate, PETA) reservoir. Inside the 3D printed polymer reservoir, platinum (Pt) electrodes, that are further routed over the reservoir walls, are laser printed by a metal reduction process. The transistor fabrication is completed by a second inkjet printed layer of composite solid polymer electrolyte and an organic top‐gate layer (PEDOT:PSS). This concept does not exceed annealing temperatures higher than 100 °C, and is compatible with a range of substrates. The characterized electrolyte‐gated field‐effect transistor show a reasonable on/off‐ratio in the range of 104 with negligible leakage currents. This materials and hybrid device manufacturing scheme has believed great potential for bioelectronics, lab‐on‐a‐chip applications and others. [ABSTRACT FROM AUTHOR]

With respect to efficient use of diminishing or harder to reach energy resources, the catalysis of processes that will otherwise require high overpotentials is a very important application in today's world. As a newly developed class of materials, high‐entropy sulfides (HESs) are promising electrocatalysts for a variety of different reactions. In this report, HESs containing five or six transition metals are synthesized in a one‐step mechanochemical process. Seven HESs of Pnma (M:S≈1:1) and three Pa‐3 (M:S = 1:2) structures are investigated as electrocatalysts for the oxygen evolution reaction (OER). The performances and properties of the HESs with different compositions and structures are compared with each other and with commercial IrO2 as reference material, in terms of OER overpotential, Tafel slope, electrochemically active surface area, ionic conductivity, and durability. The structural and chemical properties of these HESs are determined by X‐ray diffraction, transmission electron microscopy, scanning electron microscopy, X‐ray photoelectron spectroscopy, and energy‐dispersive X‐ray spectroscopy. Most of the HESs show excellent and promising performance as OER electrocatalysts under alkaline conditions, and outperform the reference OER catalyst IrO2. [ABSTRACT FROM AUTHOR]

High‐throughput (HT) synthesis and HT characterization techniques are becoming increasingly important due to the ever‐increasing complexity of materials and applications of advanced functional compounds. This work reports on the high‐throughput compilation of material libraries of high‐entropy oxides with fluorite crystal structure and tunable band gaps to be used as, e.g., semiconductors for photovoltaic applications. The material libraries cover the high‐entropy range of rare‐earth oxides with 5, 6, and 7 different cations (Ce, La, Sm, Pr, Tb, Y, and Zr) in near equimolar concentrations, but also the medium entropy range with 4 cations. The atmosphere used during or after synthesis is found to have a large effect on the band gap of these materials. Multivalent rare‐earth cations such as Ce/Pr/Tb enable reversible tuning of the band gap between 2.0 and 3.5 eV upon calcination under various oxidizing and reducing atmospheres. The high‐entropy fluorite oxides with smaller band gaps exhibit high electron mobility and transport energy levels compatible with common solar cell architectures. [ABSTRACT FROM AUTHOR]

Printed electronic devices have demonstrated their applicability in complex electronic circuits. There is recent progress in the realization of neuromorphic computing systems (NCSs) to implement basic synaptic functions using solution-processed materials. However, a fully printed neuron is yet to be realised. We demonstrate a fully printed artificial neuromorphic circuit on flexible polyimide (PI) substrate. Characteristic features of individual components of the printed system were guided by the software training of the NCS. The printing process employs graphene ink for passive structures and In 2 O 3 as active material to print a two-input artificial neuron on PI. To ensure a small area footprint, the thickness of graphene film is tuned to target a resistance and to obtain conductors or resistors. The sheet resistance of the graphene film annealed at 300 °C can be adjusted between 200 Ω and 500 k Ω depending on the number of printed layers. The fully printed devices withstand a minimum of 2% tensile strain for at least 200 cycles of applied stress without any crack formation. The area usage of the printed two-input neuron is 16.25 mm 2 , with a power consumption of 37.7 mW, a propagation delay of 1 s, and a voltage supply of 2 V, which renders the device a promising candidate for future applications in smart wearable sensors. [ABSTRACT FROM AUTHOR]

This article, published in Advanced Functional Materials, discusses the development of an inkjet-printed tungsten oxide memristor that exhibits non-volatile memory and neuromorphic properties. The researchers, led by Jasmin Aghassi-Hagmann, demonstrate that the memristor can function as a high conductive state with a grown filament, making it suitable for non-volatile memory applications. Additionally, the memristor can be used as an interfacial type device for neuromorphic learning and signal processing. The authors suggest that these features can be integrated into novel printed electronic circuit architectures. [Extracted from the article]

A versatile liquid metal (LM) printing process enabling the fabrication of various fully printed devices such as intra‐ and interconnect wires, resistors, diodes, transistors, and basic circuit elements such as inverters which are process compatible with other digital printing and thin film structuring methods for integration is presented. For this, a glass capillary‐based direct‐write method for printing LMs such as eutectic gallium alloys, exploring the potential for fully printed LM‐enabled devices is demonstrated. Examples for successful device fabrication include resistors, p–n diodes, and field effect transistors. The device functionality and easiness of one integrated fabrication flow shows that the potential of LM printing is far exceeding the use of interconnecting conventional electronic devices in printed electronics. [ABSTRACT FROM AUTHOR]

In this Letter, we report an inkjet-printed resistive switching device based on an Ag/ZnO/Au structure. The device exhibits bipolar resistive switching behavior, a low operation voltage of about 0.7 V, a high on/off ratio of 107, a long retention time exceeding 104 s, and good endurance. The conduction mechanism of the device in low and high resistive states was studied and showed good consistency with the theory of Ohmic and space charge limited conduction mechanisms, respectively. [ABSTRACT FROM AUTHOR]

Effective medium theories (EMT) are powerful tools to calculate sample averaged thermoelectric material properties of composite materials. However, averaging over the heterogeneous spatial distribution of the phases can lead to incorrect estimates of the thermoelectric transport properties and the figure of merit ZT in compositions close to the percolation threshold. This is particularly true when the phases' electronic properties are rather distinct leading to pronounced percolation effects. The authors propose an alternative model to calculate the thermoelectric properties of multi‐phased materials that are based on an expanded nodal analysis of random resistor networks (RRN). This method conserves the information about the morphology of the individual phases, allowing the study of the current paths through the phases and the influence of heterogeneous charge transport and cluster formation on the effective material properties of the composite. The authors show that in composites with strongly differing phases close to the percolation threshold the thermoelectric properties and the ZT value are always dominated exclusively by one phase or the other and never by an average of both. For these compositions, the individual samples display properties vastly different from EMT predictions and can be exploited for an increased thermoelectric performance. [ABSTRACT FROM AUTHOR]

Emerging applications in soft robotics, wearables, smart consumer products or IoT-devices benefit from soft materials, flexible substrates in conjunction with electronic functionality. Due to high production costs and conformity restrictions, rigid silicon technologies do not meet application requirements in these new domains. However, whenever signal processing becomes too comprehensive, silicon technology must be used for the high-performance computing unit. At the same time, designing everything in flexible or printed electronics using conventional digital logic is not feasible yet due to the limitations of printed technologies in terms of performance, power and integration density. We propose to rather use the strengths of neuromorphic computing architectures consisting in their homogeneous topologies, few building blocks and analog signal processing to be mapped to an inkjet-printed hardware architecture. It has remained a challenge to demonstrate non-linear elements besides weighted aggregation. We demonstrate in this work printed hardware building blocks such as inverter-based comprehensive weight representation and resistive crossbars as well as printed transistor-based activation functions. In addition, we present a learning algorithm developed to train the proposed printed NCS architecture based on specific requirements and constraints of the technology. [ABSTRACT FROM AUTHOR]

Unlike nanoscale silicon transistors, printed thin-film transistors usually rely on micrometer size channel lengths. The device dimensions, the morphology of the channel material, and the interface properties strongly influence important device parameters such as the threshold voltage (Vth) and the transconductance parameter (k). In this article, we analyze and model the dependence of critical electrical device properties of printed, electrolyte-gated transistors, based on crystalline indium oxide channel, for various device geometries. It is shown that the threshold voltage scales with the charge density at the electrolyte channel interface and is hence linearly dependent on the channel length (L). Furthermore, nonlinear scaling effects in the transconductance parameter and in the ON-current are studied, which turn out to be dependent on both, channel width and length. Finally, we present a scaling model capturing the width/length dependencies of the studied transistor technology which enables the correct simulation of logic gates. [ABSTRACT FROM AUTHOR]

This article, published in Angewandte Chemie International Edition, discusses the application of the high-entropy approach to develop robust cathodes for sodium-ion batteries. The authors demonstrate that increased configurational entropy leads to enhanced performance by suppressing phase transitions and mitigating gas evolution. The article also includes research on electrocatalysis, organic synthesis, covalent organic frameworks, and separation membranes. The information provided in this article can be valuable for library patrons conducting research on these specific topics. [Extracted from the article]

This article, published in Angewandte Chemie, discusses the application of the high-entropy approach to develop robust cathodes for sodium-ion batteries. The researchers demonstrate that increased configurational entropy leads to enhanced performance by suppressing phase transitions and mitigating gas evolution. The article also includes research on electrocatalysis, organic synthesis, covalent organic frameworks, and separation membranes. The authors provide valuable insights into these topics, making it a useful resource for library patrons conducting research in these areas. [Extracted from the article]

Hybrid systems, unifying printed electronics with silicon‐based technology, can be seen as a driving force for future sensor development. Especially interesting are sensing elements based on printed devices in combination with silicon‐based high‐performance electronics for data acquisition and communication. In this work, a hybrid system integrating a solution‐processed organic photodiode in a silicon‐based system environment, which enables flexible device measurement and application‐driven development, is presented. For performance evaluation of the integrated organic photodiode, the measurements are compared to a silicon‐based counterpart. Therefore, the steady state response of the hybrid system is presented. Promising application scenarios are described, where a solution‐processed organic photodiode is fully integrated in a silicon system. [ABSTRACT FROM AUTHOR]

Rectifiers are vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode’s p-n-junction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 k Ω. Furthermore, experiments show that the circuit can work with an input amplitude down to 500mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications. [ABSTRACT FROM AUTHOR]

In many application domains, in particular automotives, guaranteeing a very low failure rate is crucial to meet functional and safety standards. Especially, reliable operation of memory components such as SRAM cells is of essential importance. Due to aggressive technology downscaling, process and runtime variations significantly impact manufacturing yield as well as functionality. For this reason, a thorough memory failure rate assessment is imperative for correct circuit operation and yield improvement. In this regard, Monte Carlo (MC) simulations have been used as the conventional method to estimate the variability induced failure rate of memory components. However, MC methods become infeasible when estimating rare events such as high-sigma failure rates. To this end, importance sampling (IS) methods have been proposed which reduce the number of required simulations substantially. However, existing methods still suffer from inaccuracies and high computational efforts, in particular for high-sigma problems. In this article, we fill this gap by presenting an efficient mixture IS approach based on Bayesian optimization, which deploys a surface model of the objective function to find the most probable failure points. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and the higher trustworthiness of the estimated failure rate by accurately exploring the design space. The approach is evaluated on a 6T-SRAM cell as well as a master–slave latch based on a 28-nm FDSOI process. The results show an improvement in accuracy, resulting in up to 63 × better accuracy in estimating failure rates compared to the best state-of-the-art solutions on a 28-nm technology node. [ABSTRACT FROM AUTHOR]

In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In2O3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al2O3), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al2O3 as the dielectric in the FETs, our devices show electrolyte-type gating behavior. This is a result from the formation of protons on the Al2O3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance. [ABSTRACT FROM AUTHOR]

Printed and flexible metal-oxide transistor technology has recently demonstrated great promise due to its high performance and robust mechanical stability. Herein, fully printed inverter structures using electrolyte-gated oxide transistors on a flexible polyimide (PI) substrate are discussed in detail. Conductive graphene ink is printed as the passive structures and interconnects. The additive printed transistors on PI substrates show an Ion=Ioff ratio of 106 and show mobilities similar to the state-of-the-art printed transistors on rigid substrates. Printed meander structures of graphene are used as pull-up resistances in a transistor-- resistor logic to create fully printed inverters. The printed and flexible inverters show a signal gain of 3.5 and a propagation delay of 30 ms. These printed inverters are able to withstand a tensile strain of 1.5% following more than 200 cycles of mechanical bending. The stability of the electrical direct current (DC) properties has been observed over a period of 5 weeks. These oxide transistor-based fully printed inverters are relevant for digital printing methods which could be implemented into roll-to-roll processes. [ABSTRACT FROM AUTHOR]

Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor–resistor logic has been employed so far, but depletion- and enhancement-mode EGTs in a transistor–transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~2 × for the gain and oscillation frequency, in comparison with the resistor–transistor logic design. Moreover, the power consumption is reduced by 6 ×. [ABSTRACT FROM AUTHOR]

Morphological transition of a rod-shaped phase into a string of spherical particles is commonly observed in the microstructures of alloys during solidification (Ratke and Mueller, 2006). This transition phenomenon can be explained by the classic Plateau-Rayleigh theory which was derived for fluid jets based on the surface area minimization principle. The quintessential work of Plateau-Rayleigh considers tiny perturbations (amplitude much less than the radius) to the continuous phase and for large amplitude perturbations, the breakup condition for the rod-shaped phase is still a knotty issue. Here, we present a concise thermodynamic model based on the surface area minimization principle as well as a non-linear stability analysis to generalize Plateau-Rayleigh's criterion for finite amplitude perturbations. Our results demonstrate a breakup transition from a continuous phase via dispersed particles towards a uniform-radius cylinder, which has not been found previously, but is observed in our phase-field simulations. This new observation is attributed to a geometric constraint, which was overlooked in former studies. We anticipate that our results can provide further insights on microstructures with spherical particles and cylinder-shaped phases. [ABSTRACT FROM AUTHOR]

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– 10 μF cm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices. [ABSTRACT FROM AUTHOR]

This article, titled "Fully Printed Electrolyte-Gated Transistor Formed in a 3D Polymer Reservoir with Laser Printed Drain/Source Electrodes," discusses the use of laser and inkjet printing methods to create microscale electronic components, specifically electrolyte-gated transistors, within 3D polymer reservoirs. The authors, Gabriel Cadilha Marques, Jasmin Aghassi-Hagmann, and their colleagues, propose that these functional 3D reservoirs could have potential applications in bioelectronic sensors. The article includes an image credit to George Mathew for his contribution to the design of the image. [Extracted from the article]

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

Electrolyte-gated field-effect transistor technology is an attractive candidate for printed low-power electronics due to its high field-effect mobility and extremely low-voltage operation. Relying on an additive process, inkjet-printed devices display large process variations due to ink-substrate interactions, sensitivity to environmental conditions, such as temperature and humidity, as well as intrinsic variations of the ink. All of these sources of variations may display themselves in non-Gaussian distributions as suggested by our experiments. In this paper, we therefore propose a generic methodology for variability modeling of printed transistors, based on the Gaussian mixture model, which can be used to model any arbitrary distribution of the transistor model parameters. The proposed methodology was tested on two different data sets and has been used to predict the behavior of a measured printed security circuit as well as transistor dc characteristics. [ABSTRACT FROM AUTHOR]

A printed electronics technology has the advantage of additive and extremely low-cost fabrication compared with the conventional silicon technology. Specifically, printed electrolyte-gated field-effect transistors (EGFETs) are attractive for low-cost applications in the Internet-of-Thingsdomain as they can operate at lowsupply voltages. In this paper, we propose an empirical dc model for EGFETs,which can describe the behavior of the EGFETs smoothly and accurately over all regimes. The proposed model, built by extending the Enz--Krummenacher--Vittoz model, can also be used to model process variations,which was not possible previously due to fixed parameters for near threshold regime. It offers a single model for all the operating regions of the transistors with only one equation for the drain current. Additionally, it models the transistors with a less number of parameters but higher accuracy compared with existing techniques. Measurement results from several fabricated EGFETs confirm that the proposed model can predict the I-V more accurately compared with the state-of-the-art models in all operating regions. Additionally, the measurements on the frequency of a fabricated ring oscillator are only 4.7% different from the simulation results based on the proposed model using values for the switching capacitances extracted from measurement data, which showsmore than 2x improvement comparedwith the state-of-the-art model. [ABSTRACT FROM AUTHOR]

Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ~2V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ~4 and 2.3 ms propagation delay time at 1V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6V with a frequency of ~255 Hz and can reach frequencies up to ~350 Hz at 2V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits. [ABSTRACT FROM AUTHOR]

The cover image (referring to article number 2000252 by Surya Abhishek Singaraju, Jasmin Aghassi‐Hagmann, and co‐workers) depicts fully printed inverters in a transistor‐resistor logic on flexible polyimide substrates. Polycrystalline indium oxide is printed as the active semiconducting material whereas graphene is printed as the passive structures. The authors observed the devices to be highly stable in electrical performance while withstanding tensile strain of more than 2%. A polymer electrolyte is used as gate insulator and PEDOT:PSS as top gate. The devices are even subjected to stretching in order to substantiate the surface corrugation of the printed films. [ABSTRACT FROM AUTHOR]

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches. [ABSTRACT FROM AUTHOR]