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Bistability in the current–voltage characteristics of semiconductor superlattices and quantum cascade laser structures has the potential for wide-ranging applications, particularly in sensing systems. However, the interdependency of applied bias and current injection in conventional two-terminal structures has led to complications in analysis and rendered the bistability phenomenon difficult to implement in practical applications. Here, we report a new kind of electronic bistability coupled to optical switching in a resonant tunneling bipolar superlattice transistor. This bistability manifests as sharp discontinuities in the collector current with extremely small variations of the applied voltage, which arise from unstable tunneling transmission across the hetero-barrier between the two-dimensional electron gas (2DEG) at the edge of the transistor base and the collector superlattice structure. The electronic transitions between high and low quantum mechanical transmissions are demonstrated to be caused by self-consistent variations of the internal electric field at the heterointerface between the 2DEG and the superlattice. They are also present in the base current of the three-terminal device and result in sharp switching of near-infrared spontaneous light emission output from an interband radiative recombination process with a peak emission wavelength of 1.58 μ m. A comprehensive quantum mechanical theoretical model accounting for the self-consistent bistable tunneling transmission is in quantitative agreement with the experimental data. The measured peak transconductance sensitivity value of 6000 mS can be used in the highly sensitive detector and non-linear device applications. [ABSTRACT FROM AUTHOR]

The intrinsic carrier density of 4H-SiC at temperatures ranging from 294 to 595 K was derived by analyzing a collector current in an npn-type SiC bipolar junction transistor, the structure of which was designed based on a device simulation. The obtained intrinsic carrier density was in good agreement with the value calculated from the bandgap and effective densities of states taking multiple and non-parabolic SiC bands into account. The coincidence of the intrinsic carrier density obtained by these two different approaches indicates the usefulness of the proposed method and the validity of the evaluated value of intrinsic carrier density. The temperature dependence of the bandgap was also estimated from the deduced intrinsic carrier density and compared with an empirical formula. The derived bandgap agreed well with the empirical formula showing bandgap shrinkage at high temperatures. The errors in evaluating the intrinsic carrier density and the bandgap caused by the estimation of the hole density and electron mobility in the base layer are also discussed for the proposed method. [ABSTRACT FROM AUTHOR]

Due to the erratic switching phenomenon of the Si avalanche bipolar junction transistor (ABJT) in the Marx bank circuit (MBC), an explanation of the leakage current trigger mode in the overvoltage state with a lack of displacement current is proposed. There are random switching properties (i.e., switching or non-switching) in the ABJT with emitter–base shorted, triggered by a voltage ramp to the overvoltage state temporarily with dV/dt rate close to 0 V/ns. The experimental conditions and characteristics of erratic behaviors are summarized. The optical visualization of the current channel in an erratic switching state is obtained, and the corresponding physical model of the leakage current trigger mode is established. It shows that the switching event occurs with the change in the position of the conductive channel. The process of emitter electron injection is caused by the leakage current in the overvoltage state instead of the displacement current. Meanwhile, the intensity of this trigger mode is weak, and the instability of the leakage current may cause the failure of switching. The study of erratic switching is of great significance for the working reliability of MBCs and failure analysis of ABJTs. The proposed explanation is validated by the agreement between the simulation results and the experimental observations. [ABSTRACT FROM AUTHOR]

In this work, a novel high current capability gallium nitride (GaN) tri-gate power device with an integrated parasitic bipolar junction transistor (BJT) is proposed to enhance its static electrical characteristics. The device's electrical characteristics are thoroughly studied and analyzed using 3D technology computer-aided design simulation tools. The two-dimensional electron gas channel is effectively pinched off in the off-state due to the depletion region induced by side-gate metals and parasitic BJT, resulting in a positive threshold voltage (V TH) and enhanced mode (E-mode) operation. The parasitic BJT provides an additional conductive channel in the on-state, significantly improving the output current capability. Compared with the conventional tri-gate (C-Trigate) device, the proposed high current capability GaN trigate (HC-Trigate) device boosts saturation output current by nearly a factor of three under identical conditions, reaching 1,761 mA mm−1. The 3D simulation shows the proposed GaN HC-Trigate power device features a positive V TH of 1.1 V, a low specific on-resistance (R on,sp) of 0.18 mΩ*cm2 at breakdown voltage of 760 V, and the Baliga's figure of merit of 3.21 GW cm−2. Furthermore, the GaN HC-Trigate power device exhibits superior thermal performance and switching characteristics, indicating its great potential for power electronics applications. [ABSTRACT FROM AUTHOR]

ABSTRACT The insulated gate bipolar transistor (IGBT) is one of the most important power semiconductor devices in power electronics and is also prone to failure. High junction temperature and junction temperature fluctuation of IGBT are the main causes of IGBT module aging failure. The high‐precision monitoring of the junction temperature of the IGBT module is a prerequisite for IGBT life prediction, which is crucial for reducing maintenance costs and improving equipment reliability. Therefore, an IGBT junction temperature estimation method based on long short‐term memory (LSTM) neural network and sliding window estimation model is proposed and applied in practical industrial scenarios. This method uses the operating data of the motor drive device in the actual industrial application scenario as the training and test data set and uses the external operating parameters of the IGBT module to estimate the junction temperature of the IGBT module. Compared with the internal operating parameters of the IGBT module based on switching transient, the external operating parameters are easier to collect and process, and more suitable for practical application scenes. A sliding window estimation model is proposed to estimate the junction temperature of the IGBT module. Compared with the point‐to‐point estimation method, the sliding window estimation method can capture the influence of historical operation data better and has a higher capability of time series data estimation. The IGBT junction temperature estimation of sliding windows is realized by the LSTM neural network, which is more suitable for time series estimation in real industrial scenarios. The experimental results show that the estimation accuracy of the sliding window estimation method is better than that of the point‐to‐point estimation method, and the accuracy of the sliding window estimation method based on LSTM is better than that of the sliding window estimation method based on other machine learning models. It proves that the proposed method can better capture the dynamic process of the system and has higher estimation accuracy. [ABSTRACT FROM AUTHOR]

Stacking faults in silicon carbide have been widely studied due to their negative impact on the application of silicon carbide in the power electronics industry. In this work, with the assistance of forward biasing, we observe several triangular shaped structures emerging near the indenter imprint in two separate 4H–SiC bipolar junction transistor samples that were deformed by nanoindentation. Based on the study of electroluminescence spectra on one of the samples, the emission peak at 420 nm indicates the formation of single Shockley stacking faults inside deformed transistors. We conclude that the use of indentation can provide a method to study recombination induced stacking faults in silicon carbide junction devices by intentionally introducing dislocations at selected areas of interest. [ABSTRACT FROM AUTHOR]

Summary: A current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV. [ABSTRACT FROM AUTHOR]

Neutron and γ-ray irradiation damages to transistors are found to be non-additive, and this is denoted as the irradiation synergistic effect (ISE). Its mechanism is not well-understood. The recent defect-based model [Song and Wei, ACS Appl. Electron. Mater. 2, 3783 (2020)] for silicon bipolar junction transistors (BJTs) achieves quantitative agreement with experiments, but its assumptions on the defect reactions are unverified. Going beyond the model requires directly representing the effect of γ-ray irradiation in first-principles calculations, which was not feasible previously. In this work, we examine the defect-based model of the ISE by developing a multiscale method for the simulation of the γ-ray irradiation, where the γ-ray-induced electronic excitations are treated explicitly in excited-state first-principles calculations. We find the calculations agree with experiments, and the effect of the γ-ray-induced excitation is significantly different from the effects of defect charge state and temperature. We propose a diffusion-based qualitative explanation of the mechanism of positive/negative ISE in NPN/PNP BJTs in the end. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiple-input single-output current-mode shadow filter and oscillator using current-controlled current conveyors (CCCIIs). The CCCII current gains are used to set the filter's quality factor and natural frequency. The filter is resistorless with grounded capacitors, making it more suitable for integration. The filter offers low-pass, high-pass, band-pass, band-stop and all-pass transfer functions in a single topology by appropriately applying the input signals. To validate the functionality of the new topology, the proposed circuit is simulated by SPICE using bipolar transistors arrays AT&T ALA400-CBIC-R. [ABSTRACT FROM AUTHOR]

The LM2990-integrated circuit family was among the first low-dropout voltage regulators to use a coupling diode to reduce a quiescent current. In certain conditions, the coupling diode, connected between the output terminal and the driver transistor collector contact, activates to supply the serial power transistor base current from the load. Nonetheless, an indirect characterization of the serial NPN transistor was affected, making it difficult to estimate its forward emitted current gain and a base current as a function of the absorbed total ionizing dose. The original SPICE simulation model had some limitations with generating the faithful simulation of radiation effects in samples supplied with a non-ideal voltage source. Therefore, a novel four-step computer simulation method was developed to specify bias and load conditions when the coupling diode reaction would not negatively affect the characterization of the serial power transistor. The previously reported method for estimating the serial transistor base current could be successfully used for dropout voltages that slightly exceed three equivalent diode voltage drops (that is, 2.4V) at the base-emitter junctions of the output amplifier transistors. [ABSTRACT FROM AUTHOR]

A coupling model is established on piezoelectric semiconductor bipolar junction transistors (PS-BJT) subjected to mechanical loadings by abandoning depletion layer approximation and low injection assumption. Effect of base region on device performance and interaction between emitter/base junction (E/B) and base/collector junction (B/C) are investigated. It is found that too small a base width will cause B/C to extract electrons directly from emitter region, implying that an electron passageway will be excited to link from collector- to emitter-region by striding over base-region (abbreviated as "EP-CE" hereafter). We particularly clarify that the current produced by electrons flowing across EP-CE is independent of electron-hole recombination in E/B, which means that this current has not yet been bestowed on the information of base current. "Information of base current" refers to dispatching information of base current on the electrons in emitter region. Thus, a current from EP-EC cannot be reckoned in the amplification effect of base current. Our investigations show that base width should not be designed too small to avoid EP-CE, which has not been revealed before. As regards to tuning PS-BJT performance by mechanical loadings, we revealed the mechanism as follows: 1) raising electron-hole recombination rate inside E/B to reduce resistivity such that more electrons can be driven from emitter- to base-region; 2) elevating electron conductivity in base-region for easier pass of electrons; 3) promoting attractive ability of B/C on electrons such that more electrons cross the interface. Numerical results show that transmission characteristics can be greatly increased as expected by mechanical tuning. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated stacked architecture to address the challenges of 6G application using CMOS analog pre-distortion and tunable neutralization techniques. By using this method for the stacked power amplifier design, a baseband and passband impedance transformation is achieved, that combined with the stacked power amplifier architecture allows for high efficiency in deep back off, with a reduced load modulation for high bandwidth. This project designs an efficient Stacked Power Amplifier (PA) for 6G. The power amplifier is implemented in 180nm CMOS technology using Cadence and ADS tool. The usage of a diode pre-distorter for analog pre-distortion is investigated for the stacked power amplifier design. It is shown that the linearity of the stacked power amplifier has been significantly improved compared to a bipolar transistor at almost no additional layout size. This research work presents design of a Ka band power amplifier for sixth generation (6G) mobile communication in CMOS design. The stacked power amplifier consists of two different stages of architecture. With 5-volt supply, the stacked power amplifier achieves a small-signal gain of 16 dB, saturated output power (Psat) of 18 dBm, and achieves the maximum power added efficiency of 34.79%. The amplifier has been designed in 180-nm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents an innovative technique, Advanced Predictor of Electrical Parameters, based on machine learning methods to predict the degradation of electronic components under the effects of radiation. The term degradation refers to the way in which electrical parameters of the electronic components vary with the irradiation dose. This method consists of two sequential steps defined as 'recognition of degradation patterns in the database' and 'degradation prediction of new samples without any kind of irradiation'. The technique can be used under two different approaches called 'pure data driven' and 'model based'. In this paper, the use of Advanced Predictor of Electrical Parameters is shown for bipolar transistors, but the methodology is sufficiently general to be applied to any other component. [ABSTRACT FROM AUTHOR]

Two-dimensional layered materials, characterized by their atomically thin thicknesses and surfaces that are free of dangling bonds, hold great promise for fabricating ultrathin, lightweight, and flexible bipolar junction transistors (BJTs). In this paper, a van der Waals (vdW) BJT was fabricated by vertically stacking MoS2, WSe2, and MoS2 flakes in sequence. The AC characteristics of the vdW BJT were studied for the first time, in which a maximum common emitter voltage gain of around 3.5 was observed. By investigating the time domain characteristics of the device under various operating frequencies, the frequency response of the device was summarized, which experimentally proved that the MoS2/WSe2/MoS2 BJT has voltage amplification capability in the 0–200 Hz region. In addition, the phase response of the device was also investigated. A phase inversion was observed in the low-frequency range. As the operating frequency increases, the relative phase between the input and output signals gradually shifts until it is in phase at frequencies exceeding 2.3 kHz. This work demonstrates the signal amplification applications of the vdW BJTs for neuromorphic computing and wearable healthcare devices. [ABSTRACT FROM AUTHOR]

A bipolar junction transistor (BJT) and its operation are fundamental concepts for the understanding of power electronics (industrial electronics), transistor-transistor logic (TTL), electronic switching, and signal amplification in modern electronics. Previous research showed that non-major engineering, computer, electronic, and electrical engineering students could not understand the basic concepts involved in a BJT. This paper describes the development of a two-tier diagnostic test, the test's administration, limitations, the participants' detailed context, and findings from a study that explores Myanmar and Thai second-year undergraduate students' understanding of BJT working principles and applications. The results revealed that many students in both countries had the same alternative conceptions about collector current in each operation mode of the BJT. Some alternative conceptions differ from the previous research, such as a) the collector current does not depend on the base current in cut-off mode, and b) changing the collector current does not depend on the base current in active mode, but it depends on the collector supply voltage. These research findings provide valuable information and instruments for teachers to insight, prevent, and correct the alternative conceptions proposed by students. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) materials have attracted great attention in the past few years and offer new opportunities for the development of high-performance and multifunctional bipolar junction transistors (BJTs). Here, a van der Waals BJT based on vertically stacked n+-MoS2/WSe2/MoS2 was demonstrated. The electrical performance of the device was investigated under common-base and common-emitter configurations, which show relatively large current gains of α ≈ 0.98 and β ≈ 225. In addition, the breakdown characteristics of the vertically stacked n+-MoS2/WSe2/MoS2 BJT were investigated. An open-emitter base-collector breakdown voltage (BVCBO) of 52.9 V and an open-base collector-emitter breakdown voltage (BVCEO) of 40.3 V were observed under a room-temperature condition. With the increase in the operating temperature, both BVCBO and BVCEO increased. This study demonstrates a promising way to obtain 2D-material-based BJT with high current gains and provides a deep insight into the breakdown characteristics of the device, which may promote the applications of van der Waals BJTs in the fields of integrated circuits. [ABSTRACT FROM AUTHOR]

A Reverse Conduction Insulated Gate Bipolar Transistor (RC-IGBT) featuring an Active Trench Barrier (ATB) based on Super-Junction (SJ) technology is proposed and investigated. The double-trench gates are designed at the N-pillar and P-pillar of the SJ drift. Consequently, a p-type ATB located between the two trench gates is formed. The ATB working mechanism is controlled and modulated by the Gate Voltage (VGE) of the double-trench gates. In the forward conduction state, the ATB channel is depleted and automatically pinched off by the positive VGE. Thus, the barrier potential of the ATB is remarkably improved. Additionally, holes accumulate underneath the ATB and maintain high conductivity modulation of the SJ drift region. Thus, the low on-state voltage drop (VON) is obtained. In the reverse conduction state, the ATB pinch-off effect automatically fades away with the grounded VGE. In addition, the ATB, P-pillar, and N + act as the anode, drift, and cathode of the Free-Wheeling Diode (FWD), respectively. Electrons are blocked and accumulated by the trench gates. Thus, the hole injection is enhanced and the reverse conduction voltage (VR) is reduced. In the turn-off state, excessive holes can be effectively extracted by the extra ATB channel, and the turn-off loss (EOFF) is remarkably decreased. As a result, the trade-off relationship between VON and EOFF can be significantly improved, which achieves the best comprehensive property when compared with the conventional RC-IGBT and SJ-IGBT. [ABSTRACT FROM AUTHOR]

A model is proposed to explain the low-dose-rate effects when exposed to ionizing radiation in bipolar structures, taking into account the effects of the subthreshold defect formation in highly doped silicon layers. Variants for the degradation of the base current in a bipolar transistor are considered, taking into account the simultaneous action of surface radiation and displacement effects in the near-surface base region. The conditions for the enhanced low-dose-rate sensitivity (ELDRS) in bipolar structures are shown. The presented results of the analysis allow us to explain most of the observed experimental results. [ABSTRACT FROM AUTHOR]

In this study, the ringing phenomenon of gallium nitride‐field effect transistor (GaN‐FET) and silicon‐insulated gate bipolar transistor (Si‐IGBT) inverter excitations in a ring sample was thoroughly measured and analyzed by using a high‐quality oscilloscope with a very high sampling rate of 5 giga‐samples per second (GS/s). Owing to the rapid switching of the GaN‐FET power devices in several nanoseconds and the ringing frequencies in the MHz range, the use of the high sampling rate of 5 GS/s is necessary and useful for accurate measurement. The experimental findings and analysis reveal the following three key points: (i) there are two possible types of high‐frequency resonance phenomena, that is, the first one caused by semiconductor devices and circuits and the other generated by the resonance with loads in use. (ii) The ringing phenomenon because of the resonance under the load is considered to be due to the rising time of pulses that are caused by the rapid switching of the semiconductor devices. (iii) The ability to measure and the two types of ringing phenomena depends on the intensity of the white noise of the measuring instrument [ABSTRACT FROM AUTHOR]

Summary: Bipolar junction transistors (BJTs) are widely used in various electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for BJTs is crucial for EMC analysis of these systems, such as high‐frequency circuits. In this paper, a BJT EMC model that satisfies both functionality and EMC analysis requirements was established based on physical characteristic measurement. First, comprehensive and systematic methods for measurement and extracting SPICE parameters based on physical BJTs are presented, including a proposed curve‐fitting calculation method for extracting barrier capacitance parameters. Second, an analysis of the impact of major BJT electrical characteristics parameters was conducted, leading to the identification of important model parameters affecting BJT functionality and EMC. Finally, the primary BJT model was optimized using the simplex method, and a method for EMC analysis and verification of the BJT model was presented. The experimental and simulation results are in good agreement, and the established model meets the accuracy requirements for both EMC and functionality. Therefore, the proposed method is feasible and suitable for the EMC modeling of BJTs. [ABSTRACT FROM AUTHOR]

A set of transfer and output current–voltage characteristics of a bipolar transistor with a short-period superlattice in the emitter region are calculated. It is shown that the presence of a superlattice in the transistor structure leads to the formation of a negative differential conductivity region, which makes it possible to implement not only amplification but also the generation and multiplication of high-frequency oscillations. [ABSTRACT FROM AUTHOR]

The high voltage–high humidity–high temperature reverse bias (HV-H3TRB) test was utilized to evaluate the reliability of silicon carbide insulated gate bipolar transistors (SiC IGBTs). Moisture invasion often induces termination/passivation and metal corrosion. Therefore, the HV-H3TRB test is generally used to assess termination / passivation robustness. However, under the HV-H3TRB test conditions, gate quality degradation may occur. In this study, the dominant degradation mechanism of SiC IGBTs was investigated. The changes of the most sensitive static characteristics (e.g., threshold voltage, breakdown voltage, and leakage current) were recorded. The threshold voltage decreased and leakage current increased substantially after > 1000 h of HV-H3TRB tests under 85 ℃/85% RH climate conditions. Capacitance–voltage (C–V) curve measurements indicated that the mobile ions at the SiC/SiO2 interface or in the gate oxide likely caused the threshold-voltage instability in the SiC IGBTs after the HV-H3TRB tests. This instability can be recovered by applying a negative gate bias. Subsequent failure analysis confirmed no corrosion of metals or termination/passivation in the device, which indicates the robustness of the passivation (consisting of phosphor-silicate glass and Si3N4). Therefore, the gate quality appears to be a significant reliability risk for SiC IGBTs under high humidity, high temperature, and high voltage conditions. [ABSTRACT FROM AUTHOR]

This paper introduces a new design of silicon nanowire (Si NW) phototransistor (PT) arrays conceived explicitly for improved CMOS image sensor performance, and comprehensive numerical investigations clarify the characteristics of the proposed devices. Each unit within this array architecture features a top-layer vertical Si NW optimized for the maximal absorption of incoming light across the visible spectrum. This absorbed light generates carriers, efficiently injected into the emitter–base junction of an underlying npn bipolar junction transistor (BJT). This process induces proficient amplification of the output collector current. By meticulously adjusting the diameters of the NWs, the PTs are tailored to exhibit distinct absorption characteristics, thus delineating the visible spectrum's blue, green, and red regions. This specialization ensures enriched color fidelity, a sought-after trait in imaging devices. Notably, the synergetic combination of the Si NW and the BJT augments the electrical response under illumination, boasting a quantum efficiency exceeding 10. In addition, by refining parameters like the height of the NW and gradient doping depth, the proposed PTs deliver enhanced color purity and amplified output currents. [ABSTRACT FROM AUTHOR]

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. [ABSTRACT FROM AUTHOR]

This paper presents the application of unscented Kalman filter (UKF) for output voltage estimation of the Darlington amplifier (DA). Implementation of UKF requires the state-space model of DA circuit, which has been obtained using Kirchhoff's voltage law (KVL), Kirchhoff's current law (KCL) and the Gummel-Poon model of the bipolar junction transistor (BJT). This work uses Kronecker product for vector multiplication. The mathematical representation of nonlinear system in terms of Kronecker product helps to reduce the computational burden involved in the vector multiplication. The proposed method has the advantage that it can be used for the nonlinear region and large amplitude input signal. As the maximal precision of estimation requires modelling in terms of circuit elements and device parameters, the proposed method is able to provide an accurate estimation. We compared the UKF estimation results with the extended Kalman filter (EKF) and iterated extended Kalman filter (IEKF). The UKF presents smaller mean square error (MSE) as compared to EKF and IEKF as UKF is accurate to the third order for any nonlinearity. In addition, IEKF presents smaller MSE as compared to EKF because the linearisation error is taken into account by IEKF. [ABSTRACT FROM AUTHOR]

The properties of a bipolar NPN transistor when exposed to unmodulated incoherent radiation created by a white LED are studied. The static and dynamic characteristics of the transistor are measured at various exposure intensities. It is shown that the change in the characteristics of the transistor under the optical effect is due to the increased lifetime of nonequilibrium charge carriers and the photovoltaic effect in PN transitions. For these reasons, the gain increases, the switching threshold decreases, and the transistor's speed increases. The results obtained are applicable both to the creation of high-speed transistors and integrated circuits of a fundamentally new type. [ABSTRACT FROM AUTHOR]

This study investigates the degradation of the silicon NPN transistor's emitter-base junction, specifically the 2N2219A model, under both forward and reverse polarization. We examine the current–voltage characteristics under the influence of 1 MeV proton irradiation at various fluencies, which are 5.3 × 10 8 , 5.3 × 10 10 , 5 × 10 11 , 5 × 10 12 , and 5 × 10 13 protons/cm², all conducted at 307 K. The experimental findings elucidate a pronounced dependency of diode parameters, including the reverse saturation current, series resistance, and the non-idealist factor, on the incident proton flow. This observation underscores that proton-induced degradation is primarily driven by displacement damage, while recorded degradation is predominantly attributed to the generation of defects and interfacial traps within the transistor resulting from exposure to high-energy radiation. Our findings indicate that the effects of irradiation align more closely with the compensation phenomenon in doping rather than its reinforcement. [ABSTRACT FROM AUTHOR]

This paper proposes a modern approach to a DC/DC converter based on silicon carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFET). In particular, SiC-based MOSFETs are designed and implemented as Class-E DC/DC converter. The converter is developed as part of a solar power tower (SPT) heliostat unit to supply DC motors under different operation loads. Simulations are presented to demonstrate the effectiveness of the drive system under various scenarios using MATLAB/Simulink. A prototype experimental setup has been built and tested for the proposed converter. The proposed system for SPT converter reduces switching losses that reflect on drive system efficiency without affecting working drive performance. An identical silicon isolated-gate bipolar junction transistor (Si-IGBT)-based converter is designed and implemented to compare the proposed converter based on SiC-MOSFET. The outcomes demonstrated that the proposed converter is more capable and efficient under high temperatures saving 12% power losses at high operating frequencies. Further, the proposed system's switching frequency is higher than the traditional Si-IGBT converter, leading to a greater reduction of power losses and improved efficiency. [ABSTRACT FROM AUTHOR]

Sub-stoichiometric molybdenum oxide (MoO x) has recently been investigated for application in high efficiency Si solar cells as a "hole selective" contact. In this paper, we investigate the electrical and light-emitting properties of MoO x -based contacts on Si from the viewpoint of realizing functional bipolar devices such as light-emitting diodes (LEDs) and transistors without any impurity doping of the Si surface. We realized diodes on n-type Si substrates using e-beam physical vapor deposition of Pd/MoO x contacts and compared their behavior to implanted p + n-Si diodes as a reference. In contrast to majority-carrier dominated conduction that occurs in conventional Schottky diodes, Pd/MoO x /n-Si diodes show minority-carrier dominated charge transport with I–V, C–V, and light-emitting characteristics comparable to implanted counterparts. Utilizing such MoO x -based contacts, we also demonstrate a lateral bipolar transistor concept without employing any doped junctions. A detailed C–V analysis confirmed the excessive band-bending in Si corresponding to a high potential barrier (> --> 0.90 V) at the MoO x /n-Si interface which, along with the observed amorphous SiO x (Mo) interlayer, plays a role in suppressing the majority-carrier current. An inversion layer at the n-Si surface was also identified comprising a sheet carrier density greater than 8.6 × 10 11 cm − 2 , and the MoO x layer was found to be conductive though with a very high resistivity in the 10 4 Ω -cm range. We refer to these diodes as metal/non-insulator/semiconductor diodes and show with our device simulations that they can be mimicked as high-barrier Schottky diodes with an induced inversion layer at the interface. [ABSTRACT FROM AUTHOR]

The effects of high total dose proton irradiation on the reliability of silicon NPN rf power bipolar junction transistor (BJT) were examined by subjecting to 1, 3, and 5 MeV protons in the dose range from 100 Krad to 100 Mrad. The electrical characteristics such as Gummel characteristics (IB, IC-VBE), excess base current (ΔIB = IBpost – IBpre), current gain (hFE), and output characteristics (IC-VCE), built-in potential (Vbi) and the effective doping concentration (Nd) were studied before and after irradiation. SRIM simulation was conducted to understand the range and energy loss of protons in the BJT structure. SRIM and experimental results infer that the proton irradiation at lower energy (1 MeV) was found to degrade the current–voltage(I-V) and capacitance–voltage (C-V) characteristics more severely than higher-energy (3 and 5 MeV) proton irradiation. Thermal annealing on irradiated devices was also conducted to study the parametric recovery of irradiated devices. [ABSTRACT FROM AUTHOR]

An ultra-low power, high accuracy BJT-based CMOS temperature sensor is presented in this paper. The temperature sensor consists of analog front end (AFE) and hybrid ADC. In AFE design, two dynamic element matching (DEM) control modules are applied to current mirrors and bipolar transistors reduce the mismatch greatly and enhance the sensitivity of the temperature sensor. A hybrid ADC that combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce the power dissipation. The proposed sensor is fabricated in a 0.18 μm CMOS process, occupying an area of 0.14 mm2. The measured results indicate that, the total current is 6.5 μA from a 1.8 V power supply, and achieves an inaccuracy of ±0.15 °C (3δ) from −40 °C to 125 °C. • The temperature sensor consists of analog front end (AFE) and hybrid ADC. • Two DEM applied to current mirrors and bipolar transistors to reduce the mismatch and enhance the sensitivity greatly. • A hybrid ADC combines ΣΔ ADC and SAR ADC is designed to provide quick conversion results and reduce power dissipation. [ABSTRACT FROM AUTHOR]

This paper presents a low-power sub-bandgap voltage reference. Here, the proportional to absolute temperature (PTAT) voltage obtained from ∆VEB is applied to a subthreshold diode-connected PMOS transistor to yield a current with a positive thermal coefficient (TC). The current is then converted back to a PTAT voltage term using another subthreshold PMOS transistor at the output path. Moreover, utilizing the bipolar transistor achieves a lower process variation VR. A trimming circuit is also applied to improve the TC against the process variation further. Low-power VR is achieved by operating all the MOSFETs under the subthreshold region. The simulation results using the standard 1.8 V, 0.18 µm CMOS process shows a nominal output voltage of 0.75 V, operating from 0.9 V to 1.8 V supply voltage while consuming 41.4 nA at room temperature. The TC is about 21.6 ppm/oC and (σVREF/μVREF) = 1.0 % over a temperature range of 0 °C to 120 °C. In addition, the proposed VR circuit is simulated without a trimming circuit resulting in a reasonable μTC = 29.1 ppm/oC and (σVREF/μVREF) = 1.3%. [ABSTRACT FROM AUTHOR]

Emerging soft ionotronics better match the human body mechanically and electrically compared to conventional rigid electronics. They hold great potential for human‐machine interfaces, wearable and implantable devices, and soft machines. Among various ionotronic devices, ionic junctions play critical roles in rectifying currents as electrical p–n junctions. Existing ionic junctions, however, are limited in electrical and mechanical performance, and are difficult to fabricate and degrade. Herein, the design, fabrication, and characterization of tough transient ionic junctions fabricated via 3D ionic microgel printing is reported. The 3D printing method demonstrates excellent printability and allows one to fabricate ionic junctions of various configurations with high fidelity. By combining ionic microgels, degradable networks, and highly charged biopolymers, the ionic junctions feature high stretchability (stretch limit 27), high fracture energy (>1000 Jm−2), excellent electrical performance (current rectification ratio >100), and transient stability (degrade in 1 week). A variety of ionotronic devices, including ionic diodes, ionic bipolar junction transistors, ionic full‐wave rectifiers, and ionic touchpads are further demonstrated. This study merges ionotronics, 3D printing, and degradable hydrogels, and will motivate the future development of high‐performance transient ionotronics. [ABSTRACT FROM AUTHOR]

A low‐power negative‐positive‐negative (NPN)‐based bandgap voltage reference (BGR) over an ultra‐wide temperature range is presented. The conventional NPN‐based BGRs cannot maintain a low‐temperature coefficient (TC) with low power consumption in an ultra‐wide temperature range due to its inherent reverse junction saturation current of NPN bipolar junction transistors (BJT) in the high‐temperature range. This work introduces a new NPN‐based BGR unaffected by such saturation current. Based on Vanguard International Semiconductor Corporation (VIS) 0.18 μm/0.15 μm complementary metal oxide semiconductor (CMOS) Bipolar‐CMOS‐DMOS (BCD) process, the BGR receives the best 1.25‐mV deviation over the temperature range of −40°C to 150°C, much less than 38.5 mV from Brokaw‐type BGR. Meanwhile, the proposed BGR with the stacked NPNs for higher output voltage was fabricated. It consumes about 2 uA from a 5‐V power supply, and its average temperature coefficient is 14.89 ppm/°C. Also, the average line sensitivity is 0.039%/V. [ABSTRACT FROM AUTHOR]

This brief paper shows that robust chaotic behavior can be detected within a tuned-collector single-stage transistor-based oscillator. The content of this work also contributes to the problem of chaos localization in simplified mathematical model of standard analog building block. Searching for chaos is performed via numerical optimization routine applied onto the principal schematic of oscillator where generalized bipolar transistor is modelled as a two-port described by impedance as well as admittance matrix. In both cases, the presence of dense chaotic attractor is proved via calculation of the largest Lyapunov exponent, while its structural stability is validated by real measurement, i.e., visualization of captured oscilloscope screenshots. [ABSTRACT FROM AUTHOR]

A 13 kV class n-channel 4H–SiC trench gate insulated gate bipolar transistor (IGBT) structure is designed based on Silvaco TCAD device simulator tool. The influence of metal/SiC and SiC MOS interface trap states on the static and dynamic characteristics of SiC IGBT devices are systematically studied. It is found that the electrical properties of SiC IGBTs are insensitive to the donor or acceptor traps at the interface of metal/SiC and the donor traps at the SiC/SiO2 interface. However, the acceptor traps at the SiC/SiO2 interface affect the electrical properties of SiC IGBTs greatly. When the acceptor trap density at the SiC/SiO2 interface (Dita) is up to the level of 1012 cm−2·eV−1, the turn-on voltage drop (VCEON) is increased gradually with the augmentation of Dita. The breakdown voltage (VBR) of the device is increased slightly. Further study of the device's turn-off characteristics shows that the turn-off loss (EOFF) is decreased with the increase in Dita but a large tail current is formed. The mechanism may be that when the electrons are injected from the N+ source region into the N− drift region, the SiC/SiO2 interfacial acceptor traps at the side wall of trench gate capture a large number of electrons. As a result, the minority carrier concentration is decreased, and the conductance modulation effect on the N− drift region is weakened. [ABSTRACT FROM AUTHOR]

We demonstrate high signal-to-noise electrically detected electron-nuclear double resonance measurements on fully processed bipolar junction transistors at room temperature. This work indicates that the unparalleled analytical power of electron-nuclear double resonance in the identification of paramagnetic point defects can be exploited in the study of defects within fully functional solid-state electronic devices. [ABSTRACT FROM AUTHOR]

A novel transistor with a graphene base embedded between two n-type silicon emitter and collector layers (graphene-base heterojunction transistor) is fabricated and characterized electrically. The base voltage controlled current of the device flows vertically from the emitter via graphene to the collector. Due to the extremely short transit time for electrons passing the ultimately thin graphene base, the device has a large potential for high-frequency RF applications. The transistor exhibits saturated output currents and a clear modulation of the collector current by means of the graphene base voltage. The vertical transfer current from the emitter via the graphene base to the collector is much lower than expected from device simulations. A comparison of the graphene-base transistor and a reference silicon n-p-n bipolar transistor is performed with respect to the main DC transistor characteristics. A common-emitter gain of larger than one has been achieved for the reference device while the graphene-base transistor so far exhibits a much lower gain. [ABSTRACT FROM AUTHOR]

The paper considers schematics of low-power Output Stages (OS) and class AB Buffer Amplifiers (BA) for analog microcircuits realized on arsenide gallium n-channel field-effect transistors with control p-n junction and arsenide gallium bipolar p-n transistors within combined processes. The developed output stages are characterized by a relatively small static current consumption (about 100-200 A), provide operation at load resistances greater than 1-2 k, and have, as a rule, an increased input resistance. The maximum values of BA output currents for the positive polarity of the output voltage (vout) are determined by the width of the JFET channel, and for the negative vout half-wave, by the base current amplification factor of the BJT. In this connection, it is recommended to use compound Darlington p-n-p transistors in BA circuits. The results of computer simulation of the amplitude characteristics of pushpull BAs in LTspice at different load resistances show that the proposed circuit solutions provide the maximum amplitudes of positive and negative output voltages, close to the supply voltages. The circuit solutions considered are recommended for use in low-power operational amplifiers, including those operating under harsh operating conditions. The novelty of the paper lies in the investigation of a family of new pushpull class AB output stages for operational amplifiers, protected by 4 Russian patents and implemented under severe circuit restrictions on the types of GaAs transistors used (nJFET and nBJT). [ABSTRACT FROM AUTHOR]

Recently, nanowire detectors have been attracting increasing interest thanks to their advantages of high resolution and gain. The potential of using nanowire detectors is investigated in this work by developing a physically based model for Indium Phosphide (InP) phototransistor as well as by performing TCAD simulations. The model is based on solving the basic semiconductor equations for bipolar transistors and considering the effects of charge distribution on the bulk and on the surface. The developed model also takes into consideration the impact of surface traps, which are induced by photogenerated carriers situated at the surface of the nanowire. Further, photogating phenomena and photodoping are also included. Moreover, displacement damage (DD) is also investigated; an issue arises when the detector is exposed to repeated doses. The presented analytical model can predict the current produced from the incident X-ray beam at various energies. The calculation of the gain of the presented nanowire carefully considers the different governing effects at several values of energies as well as biasing voltage and doping. The proposed model is built in MATLAB, and the validity check of the model results is achieved using SILVACO TCAD device simulation. Comparisons between the proposed model results and SILVACO TCAD device simulation are provided and show good agreement. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

In a high-power semiconductor power module where multiple chips are populated in parallel, the thermal imbalance problem arises. In this article, the next-generation standard high-voltage insulated-gate bipolar transistor module for high-speed railcar traction is investigated to characterize the internal thermal imbalance among paralleling chips and evaluate the impact on temperature distribution in field application. The former is accomplished by a new test algorithm with a purposely designed module sample, while the latter is achieved via an advanced electro-thermal simulation from chip level to system level. The experimentally verified thermal network among paralleling chips reveals the multiple reasons for the thermal imbalance. A comparison between the simulation and experimental results regarding the paralleling chips’ power-cycling scenario helps to confirm the effectiveness of the chip model, the thermal network, and the electro-thermal simulation approach. A further electro-thermal simulation shows that the module internal thermal imbalance can lead to significant junction temperature discrepancy among paralleling chips in traction inverter applications, which should be taken into consideration for the long-term reliability assessment. [ABSTRACT FROM AUTHOR]

Commutation failure is one of the most important factors threatening the safety of multi-infeed high voltage direct current systems. To mitigate commutation failure, we have proposed a novel hybrid line-commutated converter by adding fully controlled devices to the conventional line-commutated converter. It aims to achieve auxiliary commutation and forced commutation with the help of fully controlled devices. Based on the novel hybrid line-commutated converter topology, the study investigates how to select suitable fully controlled devices and how to design the appropriate parameters of the devices. First, this article studied the general characteristics of reverse-blocking devices, including reverse-blocking integrated gate-commutated thyristor (RB-IGCT) and asymmetrical IGCT with diode (including fast recovery diode and standard recovery diode). Then, the novel commutation principle is carefully proposed and analyzed. The comprehensive simulation results and comparison study of the novel commutation principle are conducted. Then, according to the proposed commutation principle, the voltage and current working stress of devices are illustrated. According to these, vital features of devices, including recovery speed, on-state voltage, current conduction ability, surge current, maximum turn-off current, robustness, and volume of devices, are carefully analyzed and compared. Related experiments are conducted to present the vital characteristics of devices in the equivalent operating conditions in converters. Finally, the advantages and disadvantages of RB-IGCT and IGCT with fast recovery diode and standard recovery diode are comprehensively presented, which offers valuable reference considered in engineering applications. [ABSTRACT FROM AUTHOR]

In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (V SEB) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (η) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V. • Radiation-hardened SOI LDMOS using top polysilicon and SEB failure mechanism is investigated. • The top polysilicon diode reducing the number of holes flowing to the source electrode at the same time within a certain period of time, making the distribution of hole current flowing to the source at different time points more uniform. • The device can operate at a V DS of 199 V even in high energy ions with a LET of 0.2 pC/μm. • The role of the parasitic NPN BJT is critical to the SEB tolerance of the device. [ABSTRACT FROM AUTHOR]

This paper presents a bipolar junction transistor (BJT)-based CMOS temperature sensor for high accuracy, small-scale area, and low power consumption. A structure with a feedback amplifier biasing NPN transistors, combined with dynamic element matching (DEM), is proposed to avoid the effects of errors arising from the limited current gain of substrate PNP transistors in deep-submicron processes. Moreover, the switched capacitor (SC) integrators employ two single-stage cascode amplifiers for alternating cyclic sampling and integration, effectively simplifying the circuit design and reducing the operating voltage. The proposed sensor is fabricated with a standard 180 nm CMOS process, occupying an active chip area of 0.075 mm2. It consumes 39.1 μ W of power at room temperature, operating with a supply voltage of 1.8 V. The measurements indicate that the sensor exhibits an inaccuracy of ±0.97 °C (3 σ) across the temperature range from −40 °C to 120 °C following a single-point temperature calibration. [ABSTRACT FROM AUTHOR]

In this study, we introduced trace amounts of silver and nickel into 500 μm diameter copper wires to form micro-alloyed copper wires used in insulated gate bipolar transistors (IGBT). The addition of silver and nickel enhanced the mechanical properties of the conductors and suppressed the work hardening effect, significantly improving the power cyclic lifetime. Additionally, this study conducted chlorination and high-temperature oxidation test to compare the application characteristics of the heavy micro-alloyed copper wires with pure copper wires, through tensile and bending test, as well as electrical property comparisons. Finally, Cu 50Ni (50 ppm Ni) wires were selected and nickel ceramic substrates for wire bonding to evaluate module electrical properties and bonding reliability. In the chloride test, there was no significant pitting corrosion observed in copper wire, and the micro-alloyed copper wire outperformed the pure copper wires in terms of bending lifetime and power cycling performance. In the high-temperature oxidation test, an oxide layer of cuprous oxide formed on the surface of all wires. The pure copper wire exhibited a significant increase in resistance. Notably, the micro-alloyed copper wires had better resistance to oxidation. Regarding wire bonding, the use of Cu 50Ni wires and nickel ceramic substrates reduced the diffusion rate of nickel atoms from the substrate to the copper wire, forming a thinner alloy diffusion layer. This prevented electrical degradation and achieved high bonding reliability, especially under higher bonding forces. These findings confirm that micro-alloyed copper wires are suitable for high-power applications. • The advantages of adding Ni and Ag for copper micro-alloyed wires • The anti-oxidation mechanism of copper micro-alloyed wires • Two methods of application property analysis: EFM & bending tests [ABSTRACT FROM AUTHOR]

In this paper, we have studied, designed and realized a single-transistor chaotic generator with a smooth power spectrum of about −35 dBm in frequency bandwidth up to 1 GHz. The chaos generator model is described by a continuous-time six-dimensional autonomous system assuming an exponential nonlinearity. Chaotic behavior is characterized by bifurcation diagrams, Lyapunov exponents, phase portraits of the attractors and spectra of the oscillations, using both numerical and circuit simulations. Advanced Design System (ADS)-based simulations were carried out to support the theoretical analysis, and to validate the mathematical model. The simulations are carried out using real transistor parameters and taking into account the properties of the substrate, the influence of the board topology and the characteristics of the layout material. This simulation method known as EM/Circuit Co-Simulation allows the simulation results to approach as closely as possible to those of the experiments. In the light of the positive simulation results, the proposed structure is realized to demonstrate its feasibility, and to confirm the numerical results. The prototype is manufactured and mounted on a breadboard using the surface-mount devices and BFP193 bipolar junction transistor. After realizing the generator, we pushed it further towards perfection, through the proposal and realization of a broadband amplifier, in order to gain more bandwidth to improve the spectral characteristic of the generator, which makes it promising for many communication applications such as spread spectrum communication, direct chaotic communication, etc. [ABSTRACT FROM AUTHOR]

Memristors (abbreviation of memory and resistor), introduced as the fourth fundamental electrical circuit element, remember the electric charge that flowed through it. These nonlinear elements are considered as a class of two terminal resistive devices and offers a lot of possible applications in various areas. In this article, we review the dynamical behaviour of some electrical circuits with memristors. Initially, we show that a simple circuit with a capacitor and an inductor connected to a memristor exhibits periodic and chaotic attractors. After that, we show that the known Chua circuit, with a nonlinear resistance, can generate bifurcations and chaos. Substituting the nonlinear resistance by a memristor, the modified Chua circuit exhibits coexistence of attractors. Another known circuit, the Colpitts, is made of a combination of capacitors and inductors containing a bipolar junction transistor. We show that the modified Colpitts circuit, created by substituting the transistor by a memristor, presents multistability and coexistence of many attractors. [ABSTRACT FROM AUTHOR]

The heterostructure bipolar transistor solar cell architecture offers an attractive route to realize monolithic 3-terminal perovskite/silicon tandem solar cells compatible with both-side contact Si photovoltaic technologies. Essentially, the HBT implements two counter series diodes with the common third terminal realized at the interface between the two diodes through an interdigitated contact. Concrete design solutions require optimizing the HBT multilayer stack for maximum power conversion efficiency of the intrinsic cell and designing appropriate layouts for the current collecting grid of the middle terminal. In this work, we develop a modeling framework that combines electro-optical simulations of the intrinsic tandem stack with circuit-level simulations to quantify the impact of shadow and resistive losses associated with the metal contacts on the scalability of the cell size. We present a design of a HBT with homojunction silicon bottom cell that can surpass 40% efficiency with a perovskite bandgap of 1.55 eV, i.e. much higher than the limit efficiency of a series connected tandem with the same material system. Then, we explore the implications of the middle contact in terms of interdependence between the subcells and parasitic losses, by considering a top interdigitated layout and cell architectures with both homojunction and heterojunction silicon cells. We show that in most configurations proper grid design can enable the scaling up of these devices to large areas, and that the scalability can be markedly improved, especially for the case of Si heterojunction bottom cells, by developing a layout with overlapped grids. [ABSTRACT FROM AUTHOR]

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors. [ABSTRACT FROM AUTHOR]