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In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 am design kit and a complete magnetic tunnel junction model. [ABSTRACT FROM AUTHOR]

The VHSIC hardware description language (VHDL) simulation of domain wall logic allows to validate magnetic circuits functionality early in the design stage. In this paper, we present two VHDL simulation techniques for domain wall (DW) logic. The first one, closer to the physics, uses models of components described at the behavioral level. It allows to study the basic functions and reveals the specificities of DW logic. The second one, closer to the logic, models components with logic gates and delays and it allows very fast simulation of complex circuits. [ABSTRACT FROM AUTHOR]