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The ever-increasing need for computational power in embedded devices has led to the adoption heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising software technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This article demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59 percent, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference. [ABSTRACT FROM AUTHOR]

The last few years have brought advances in computer vision at an amazing pace, grounded on new findings in deep neural network construction and training as well as the availability of large labeled datasets. Applying these networks to images demands a high computational effort and pushes the use of state-of-the-art networks on real-time video data out of reach of embedded platforms. Many recent works focus on reducing network complexity for real-time inference on embedded computing platforms. We adopt an orthogonal viewpoint and propose a novel algorithm exploiting the spatio-temporal sparsity of pixel changes. This optimized inference procedure resulted in an average speed-up of 9.1X over cuDNN on the Tegra X2 platform at a negligible accuracy loss of < 0.1% and no retraining of the network for a semantic segmentation application. Similarly, an average speed-up of 7.0X has been achieved for a pose detection DNN and a reduction of 5X of the number of arithmetic operations to be performed for object detection on static camera video surveillance data. These throughput gains combined with a lower power consumption result in an energy efficiency of 511GOp/s/W compared to 70GOp/s/W for the baseline. [ABSTRACT FROM AUTHOR]

Digital ultrasound probes integrate the analog front end in the housing of the probe handle and provide a digital interface instead of requiring an expensive coaxial cable harness to connect. Current digital probes target the portable market and perform the bulk of the processing (beamforming) on the probe, which enables the probe to be connected to commodity devices, such as tablets or smartphones, running an ultrasound app to display the image and control the probe. Thermal constraints limit the number of front-end channels as well as the complexity of the processing. This prevents current digital probes to support advanced modalities, such as vector flow or elastography, requiring high-frame-rate imaging. In this paper, we present Light Probe, a digital ultrasound probe, which integrates a 64-channel 100- $\text{V}_{\text {pp}}$ TX/RX front end, including analog-to-digital conversion (up to 32.5 MS/s at 12 bit), and is equipped with an optical high-speed link (26.4 Gb/s) providing sustainable raw samples access to all the channels, which allows the processing to be performed on the connected device without thermal power constraints. By connecting the probe to a graphics processing unit-equipped PC, we demonstrate the flexibility of software-defined B-mode imaging using conventional and ultrafast methods. We achieve plane-wave and synthetic aperture imaging with frame rates from 30 up to 500 Hz consuming between 5.6 and 10.7 W. By using a combination of power and thermal management techniques, we demonstrate that the probe can remain within operating temperature limits even without active cooling, while never having to turn the probe off for cooling, hence providing a consistent quality of service for the operator. [ABSTRACT FROM AUTHOR]

An ever-increasing number of computer vision and image/video processing challenges are being approached using deep convolutional neural networks, obtaining state-of-the-art results in object recognition and detection, semantic segmentation, action recognition, optical flow, and super resolution. Hardware acceleration of these algorithms is essential to adopt these improvements in embedded and mobile computer vision systems. We present a new architecture, design, and implementation, as well as the first reported silicon measurements of such an accelerator, outperforming previous work in terms of power, area, and I/O efficiency. The manufactured device provides up to 196 GOp/s on 3.09 \text mm^2 of silicon in UMC 65-nm technology and can achieve a power efficiency of 803 GOp/s/W. The massively reduced bandwidth requirements make it the first architecture scalable to TOp/s performance. [ABSTRACT FROM AUTHOR]

The papers in this special section focus on smart edge computing and the Internet of Things (IoT). The evolution of the (IoT) is changing the nature of edge-computing devices. Availability of novel sensor interfaces, efficient digital low power processors, and high-bandwidth low-power communication protocols have generated a perfect storm within the IoT ecosystem. Next generation IoT end-nodes have to support, in place, an increasing range of functionality: multi-sensory data processing and analysis, complex systems control strategies, and, ultimately, artificial intelligence. These new capabilities will enable disruptive innovation in wearable and implantable biomedical devices, autonomous insect-sized drones, miniaturized devices for environmental sensing and continuous monitoring of buildings, industrial machinery, power grids. As a result, we witness a paradigm shift towards computationally demanding tasks on tiny form-factor devices at extreme energy efficiency. [ABSTRACT FROM AUTHOR]

Traditional application execution assumes an error-free execution hardware and environment. Such guarantees in execution are achieved by providing guardbands in the design of microelectronic processors. In reality, applications exhibit varying degrees of tolerance to error in computations. This paper proposes an adaptive guardbanding technique to combat CMOS variability for error-tolerant (probabilistic) applications as well as traditional error-intolerant applications. The proposed technique leverages a combination of accurate design time analysis and a minimally intrusive runtime technique to mitigate Process, Voltage, and Temperature (PVT) variations for a near-zero area overhead. We demonstrate our approach on a 32-bit in-order RISC processor with full post Placement and Routing (P&R) layout results in TSMC 45 nm technology. The adaptive guardbanding technique eliminates traditional guardbands on operating frequency using information from PVT variations and application-specific requirements on computational accuracy. For error-intolerant applications, we introduce the notion of Sequence-Level Vulnerability (SLV) that utilizes circuit-level vulnerability for constructing high-level software knowledge as metadata. In effect, the SLV metadata partitions sequences of integer SPARC instructions into two equivalence classes to enable the adaptive guardbanding technique to adapt the frequency simultaneously for dynamic voltage and temperature variations, as well as adapt to the different classes of the instruction sequences. The proposed technique achieves on an average 1.6 \times speedup for error-intolerant applications compared to recent work refid="ref33"/ . For probabilistic applications, the adaptive technique guarantees the error-free operation of a set of paths of the processor that always require correct timing (Vulnerable Paths) while reducing the cost of guardbanding for the rest of the paths (Invulnerable Paths). This increases the throughput of probabilistic applications upto 1.9 \times over the traditional worst-case design. The proposed technique has 0.022% area overhead, and imposes only 0.034% and 0.031% total power overhead for intolerant and probabilistic applications respectively. [ABSTRACT FROM PUBLISHER]

Resource allocation and scheduling for multicore platforms is one of the most critical challenges in today's embedded computing. In this paper we focus on a well-known multicore platform, namely the Cell BE processor, and we address the problem of allocating and scheduling its processors, communication channels and memories, with the goal of minimizing execution time for complex data streaming applications. We propose three complete approaches that optimally solve the problem and prove optimality. The first is based on the recursive application of the Logic Based Benders decomposition, resulting in a three stage algorithm. The second is a pure CP approach while the third is a hybrid approach integrating the first two. Extensive experimental evaluation shows the features of each approach and its effectiveness on a specific instance structure. [ABSTRACT FROM AUTHOR]

Abstract: This paper examines reliable advancements in low-cost DNA- and immuno-chips. Capacitance detection was successfully chosen to develop label-free bio-chips. Probe immobilization was rigorously investigated in order to obtain reliable capacitance measurements. Protein probes immobilized by using usual alkanethiols or thiolated ssDNA probes directly immobilized on gold do not allow sufficient stable capacitance measurements. New alkanethiols improved with ethylene–glycol function are shown in this paper to be more suitable materials for capacitive bio-chip development. Atomic Force Microscopy, Quartz Crystal Microbalance, and Capacitance Measurements were used to demonstrate that ethylene–glycol alkanethiols allow high time stability, smaller errors in detection, and improved ideal behaviour of the sensing surfaces. Measured capacitance is in the range of 8–11nF/mm2 for antibody layers and close to 6nF/mm2 for DNA probes. It is in the range of 10–12nF/mm2 and of 4–6nF/mm2 for antigen and DNA detection, respectively. The percentage error in detection is highly improved and it is in the range of 11–37% and of 0,23–0,82% for antigen and DNA, respectively. The reproducibility is also improved and it is close to 0,44% for single spot measurements on ethylene–glycol alkanethiols. A molecular theory attributing these improvements to water molecules strongly coordinated by ethylene–glycol functional groups and to solution ions not entering into probe films is finally proposed. [Copyright &y& Elsevier]

Designing a power-efficient interconnection architecture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effectively handle the design complexity, it is essential to provide a computer-aided design tool support for automating this task. In this paper, we address the issue of ‘application-specific design of optimal crossbar architecture’ satisfying the performance requirements of the application and optimal binding of the cores onto the crossbar resources. We present a simulation-based design approach that is based on the analysis of the actual traffic trace of the application, considering local variations in traffic rates, temporal overlap among traffic streams, and criticality of traffic streams. Our approach is physical design aware, where the wiring complexity of the crossbar architecture is also considered during the design process. This leads to detecting timing violations on the wires early in the design cycle and to having accurate estimates of the power consumption on the wires. We apply our methodology onto several MPSoC designs, and the synthesized crossbar platforms are validated for performance by cycle-accurate SystemC simulation of the designs. The crossbar matrix power consumption values are based on the synthesis of the register transfer level models of the designs, obtained using industry standard tools. The experimental case studies show large reduction in communication architecture power consumption (45.3% on average) and total wirelength (38% on average) for the MPSoC designs when compared with traditional design approaches. The synthesized crossbar designs also lead to large reduction in transaction latencies (up to 7 ×) when compared with the existing design approaches. [ABSTRACT FROM AUTHOR]

The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this paper, an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information, is proposed. The indexing scheme is based on the selection of a subset of the address bits. With respect to similar approaches, the solution has two main strengths. First, owing to an analytical model for the conflict-miss conditions of a given trace, it provides a symbolic algorithm to compute the optimum solution (i.e., the subset of address bits to be used as cache index that minimize the number of conflict misses). Second, owing to a reconfigurable bit selector that can be programmed at run time, it allows the optimal cache indexing to fit to a given application. Results show an average reduction of conflict misses of 24%, measured over a set of standard benchmarks, and for different cache configurations. [ABSTRACT FROM AUTHOR]

Biochips are emerging as a useful tool for high-throughput acquisition of biological data and continue to grow in information quality and in discovering new applications. Recent advances include CMOS-based integrated biosensor arrays for deoxyribonucleic acid (DNA) expression analysis (Hassibi and Lee, 2005), (Schienle et al., 2004), and active research is ongoing for the miniaturization and integration of protein microarrays (Kiyonaka et al., 2004), (Rubina et al., 2003), (Scrivener et al., 2003), tissue microarrays (TMAs), (Chen et al., 2004), (Shergill et al., 2004), and fluorescence-based multiplexed cytokine immunoassays (Wang et al., 2002). The main advantages of microfluidic lab-on-a-chip include ease of use, speed of analysis, low sample and reagent consumption, and high reproducibility due to standardization and automation. Without effective data-analysis methods, however, the merit of acquiring massive data through biochips will be marginal. The high-dimensional nature of such data requires novel techniques that can cope with the curse of dimensionality better than conventional data-analysis approaches. In this paper, the authors proposed a pattern-mining method to analyze large-scale biological data obtained from high-throughput biochip experiments. In particular, when a data set is given as a matrix, the method can find patterns appearing in the form of (possibly overlapping) submatrices of the input matrix. The method exploits the techniques developed for the symbolic manipulation of Boolean functions. Leveraged by this approach, the method can find, given a data matrix, all patterns that satisfy specific input parameters. The authors tested the method with several large-scale biochip data and observed that the proposed method outperforms the alternatives in terms of efficiency and the number of patterns discovered. [ABSTRACT FROM AUTHOR]

Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption, and die area. The main challenge in SPM design is to optimally map memory locations to scratchpad locations. This paper describes an algorithm to solve such a mapping problem by means of dynamic programming applied to a synthesizable hardware architecture. The algorithm works by mapping segments of external memory to physically partitioned banks of an on-chip SPM; this architecture provides significant energy savings. The algorithm does not require any user-set bound on the number of partitions and takes into account partitioning overhead. Improving on previous solutions, execution time is polynomial in the number of memory locations, even in the most general solving policy. This has the major practical advantage of allowing an arbitrary number of scratchpad segments, something that was impossible with previous methods, whose running time is exponential to this number. Strategies to optimize memory requirements and speed of the algorithm are exploited. Additionally, we integrate this algorithm in a complete and automated design, simulation, and synthesis flow. [ABSTRACT FROM AUTHOR]

On-chip interconnection networks for future systems on chip (SoC) will have to deal with the increasing sensitivity of global wires to noise sources such as crosstalk or power supply noise. Hence, transient delay and logic faults are likely to reduce the reliability of across-chip communication. Given the reduced power budgets for SoCs, in this paper, we develop solutions for combined energy minimization and communication reliability control. Redundant bus coding is proved to be an effective technique for trading off energy against reliability, so that the most efficient scheme can be selected to meet predefined reliability requirements in a low signal-to-noise ratio regime. We model on-chip interconnects as noisy channels and evaluate the impact of two error recovery schemes on energy efficiency: correction at the receiver stage versus retransmission of corrupted data. The analysis is performed in a realistic SoC setting, and holds both for shared communication resources and for peer-to-peer links in a network of interconnects. We provide SoC designers with guidelines for the selection of energy efficient error-control schemes for communication architectures. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%. [ABSTRACT FROM AUTHOR]

Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce the memory footprint of embedded software, is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression, based on the concepts of static (using the static representation of the executable) and dynamic (using program execution traces) entropy and compare them with a state-of-the-art compression scheme, IBM's CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome of our work is that static compression is not directly related to bus traffic reduction, yet there is a trade off between static compression and dynamic compression, i.e., traffic reduction. [ABSTRACT FROM AUTHOR]

Some current and most future systems-on-chips use and will use network architectures/protocols to implement on-chip communication. On-chip networks borrow features and design methods from those used in parallel computing clusters and computer system area networks. They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements). In this paper, we analyze different routing schemes for packetized on-chip communication on a mesh network architecture, with particular emphasis on specific benefits and limitations of silicon VLSI implementations. A contention-look-ahead on-chip routing scheme is proposed. It reduces the network delay with significantly smaller buffer requirement. We further show that in the on-chip multiprocessor systems, both the instruction execution inside node processors, as well as data transaction between different processing elements, are greatly affected by the packetized dataflows that are transported on the on-chip networks. Different packetization schemes affect the performance and power consumption of multiprocessor systems. Our analysis is also quantified by the network/multiprocessor co-simulation benchmark results. [Copyright &y& Elsevier]

Portable and wearable computers can be powered by different combinations of two or more battery packs to give the user the possibility of choosing an optimal compromise between lifetime and weight/size. Recent work on battery-driven power management has demonstrated that sequential discharge is suboptimal in multibattery systems and lifetime can be maximized by distributing (steering) the current load on the available batteries, thereby discharging them in a partially concurrent fashion. Based on these observations, we formulate multibattery lifetime maximization as a continuous, constrained optimization problem, which can be efficiently solved by nonlinear optimizers. We show that significant lifetime extensions can be obtained with respect to standard sequential discharge (up to 160 percent), as well to previously proposed battery scheduling algorithms (up to 12 percent). [ABSTRACT FROM AUTHOR]

Describes the use of SystemC as a simulation environment that targets heterogeneous multiprocessor systems. Cosimulation and emulation of system-on-chip designs; Specification of hardware blocks and communication channels; Partitioning of system functionalities over a set of cores and other custom hardware.

This paper presents a method to reduce the energy of interactive systems for mixed workloads: multimedia applications that require constant output rates and sporadic jobs that need prompt responses. The authors' method divides multimedia programs into stages and inserts data buffers between them. Data buffering has three purposes: 1) to support constant output rates; 2) to allow frequency scaling for energy reduction; and 3) to shorten the response times of sporadic jobs. The authors construct frequency-assignment graphs. Each vertex represents the current state of the buffers and the frequencies of the processor. The authors develop an efficient graph-walk algorithm that assigns frequencies to reduce energy, The same method can be applied to perform voltage scaling and the combination of frequency and voltage scaling. The authors' experimental results on a StrongARM-based computer show that four discrete frequencies are sufficient to achieve nearly maximum energy saving. The method reduces the power Consuinption of an MPEG program by 46%. The authors also demonstrate a case that shortens the response time of a sporadic job by 55%. [ABSTRACT FROM AUTHOR]

Dynamic Power Management (DPM) is a design methodology aiming at reducing power consumption of electronic systems by performing selective shutdown of idle system resources. The effectiveness of a power management scheme depends critically on an accurate modeling of service requests and on the computation of the control policy. In this work, we present an online adaptive DPM scheme for systems that can be modeled as finite-state Markov chains. Online adaptation is required to deal with initially unknown or nonstationary workloads, which are very common in real-life systems. Our approach moves from exact policy optimization techniques in a known and stationary stochastic environment and it extends optimum stationary control policies to handle the unknown and nonstationary stochastic environment for practical applications. We introduce two workload learning techniques based on sliding windows and we study their properties. Furthermore, a two-dimensional interpolation technique is introduced to obtain adaptive policies from a precomputed look-up table of optimum stationary policies. The effectiveness of our approach is demonstrated by a complete DPM implementation on a laptop computer with a power-manageable hard disk that compares very favorably with existing DPM schemes. [ABSTRACT FROM AUTHOR]

The objective of this work is to create a framework for the optimization of embedded software. We present algorithms and a tool flow to reduce the computational effort of programs, using value profiling and partial evaluation. Such a reduction translates into both energy savings and average-case performance improvement, while preserving a tolerable increase of worst case performance and code size. Our tool reduces the computational effort by specializing frequently executed procedures for the most common values of their parameters. The most effective specializations are automatically searched and identified, and the code is transformed through partial evaluation. Experimental results show that their technique improves both energy consumption and performance of the source code up to more than a factor of two, in average about 35% over the original program. Also, their automatic search engine greatly reduces code optimization time with respect to exhaustive search. [ABSTRACT FROM AUTHOR]

Focuses on the System-on-chip (SoC) designs, a micronetwork used for providing integrated solutions to challenging design problems in telecommunications and other electronic domains. Use of probabilistic metrics; Comparison of the micronetworks with wide area networks; Interconnection network architecture. INSETS: Wiring Delays.;Virtex II FPGA.;SPIN Micronetwork..

Describes a software-controlled approach for minimizing energy in embedded systems for real-time multimedia processing. Discussion of variable frequency and energy optimization in embedded systems; Implementation of an energy efficient streaming multimedia algorithm; Experimental results of the proposed algorithm.

Presents information on a study which proposed a power optimization paradigm for sequential components based on the concept of computational kernel, a highly simplified logic block whose behavior mimics that of the original specification. Basic theory of computational kernels; Illustration of the kernel-based power optimization paradigm; Discussion on symbolic and approximate kernel extractions.

Introduces power management algorithms for reducing energy consumption of electronic devices. Power management based on renewal theory; Power management based on time-indexed semi-Markov decision process model; Simulation results for power managing a hard disk on a laptop and a desktop running Windows OS.

Presents information on a study which proposed a generic encoder-decoder architecture algorithm for the synthesis of encoding and decoding interface logic that minimizes the average number of transitions on heavily-loaded global bus lines. Properties of the generic encoder-decoder architecture; Experimental results; Conclusions.

Presents a study on the problem of obtaining accurate power waveforms for combinatorial and sequential circuits under typical usage patterns. Estimation of power dissipation for digital complementary metal oxide semiconductor (CMOS) circuits; Functions that can be used for constructing a power waveform; Multilevel power simulation approach used; Experimental results.

Random forests (RFs) use a collection of decision trees (DTs) to perform the classification or regression. RFs are adopted in a wide variety of machine learning (ML) applications, and they are finding increasing use also in scenarios at the extreme edge of the Internet of Things (TinyML) where memory constraints are particularly tight. This article addresses the optimization of the computational and storage costs for running DTs on the microcontroller units (MCUs) typically deployed in TinyML scenarios. We introduce three alternative DT kernels optimized for memory- and compute-limited MCUs, providing insight into the key memory-latency tradeoffs on an open-source RISC-V platform. We identify key bottlenecks and demonstrate that SW optimizations enable up to significant memory footprint and latency decrease. Experimental results show that the optimized kernels achieve up to 4.5 $\mu \text{s}$ latency, $4.8\times $ speedup, and 45% storage reduction against the widely-adopted naive DT design. We carry out a detailed performance and energy cost analysis of various optimized DT variants: the best approach requires just 8 instructions and 0.155 pJ per decision. [ABSTRACT FROM AUTHOR]

The need for high‐quality automated seizure detection algorithms based on electroencephalography (EEG) becomes ever more pressing with the increasing use of ambulatory and long‐term EEG monitoring. Heterogeneity in validation methods of these algorithms influences the reported results and makes comprehensive evaluation and comparison challenging. This heterogeneity concerns in particular the choice of datasets, evaluation methodologies, and performance metrics. In this paper, we propose a unified framework designed to establish standardization in the validation of EEG‐based seizure detection algorithms. Based on existing guidelines and recommendations, the framework introduces a set of recommendations and standards related to datasets, file formats, EEG data input content, seizure annotation input and output, cross‐validation strategies, and performance metrics. We also propose the EEG 10–20 seizure detection benchmark, a machine‐learning benchmark based on public datasets converted to a standardized format. This benchmark defines the machine‐learning task as well as reporting metrics. We illustrate the use of the benchmark by evaluating a set of existing seizure detection algorithms. The SzCORE (Seizure Community Open‐Source Research Evaluation) framework and benchmark are made publicly available along with an open‐source software library to facilitate research use, while enabling rigorous evaluation of the clinical significance of the algorithms, fostering a collective effort to more optimally detect seizures to improve the lives of people with epilepsy. [ABSTRACT FROM AUTHOR]

Presents information on a study which introduced a finite-state abstract system model for power-managed systems based on Markov decision processes. Review of dynamic power management; Description of the stochastic model; Policy optimization; Conclusions.

Presents an aggressive optimization technique which targeted combinational logic circuits. Description of the remapping approach; How a logic circuits network is optimized; Indication that a remapping tool is based on a fully symbolic algorithm, geared towards flexibilty and robustness.

Introduces a novel optimization paradigm for increasing the throughput of digital systems. Background information concerning delays in combinational circuits; How exact timing analysis can be performed efficiently using symbolic techniques based on algebraic decision diagrams (ADD); Details on telescopic unit architecture; Discussion on algorithms and heuristics for the automatic synthesis of telescopic units; Results of the experiment.

Data centers are increasing in size and complexity, and we need scalable approaches to support their automated analysis and control. Performance counters and power consumption are their key "vital signs". State-of-the-Art (SoA) monitoring systems provide built-in tools to collect performance measurements, and custom solutions to get insight on their power consumption. However, with the increase in measurement resolution (in time and space) and the ensuing huge amount of measurement data to handle, new challenges arise, such as bottlenecks on the network bandwidth, storage and software overhead on the monitoring units. To face these challenges we propose a novel monitoring platform for data centers, which enables real-time high-resolution profiling (i.e., all available performance counters and the entire signal bandwidth of the power consumption at the plug—sampling up to 20 μ s —with an error below 1%) and analytics, both at the edge (node-level analysis) and on a centralized unit (cluster-level analysis). The monitoring infrastructure is completely out-of-band, scalable, technology agnostic and low cost, and it is already installed in a SoA high-performance compute cluster (i.e., D.A.V.I.D.E. —18th in Green500 November 2017). [ABSTRACT FROM AUTHOR]

The authors of a Computer article from 2002 reflect on their proposal to use networks on chips to address scalable communications on silicon VLSI chips. [ABSTRACT FROM PUBLISHER]

Self-sustainability and intelligence will be critical features of the next generation of Internet of Things devices. Power management circuits need to be energy-efficient in multiple power modes, from nW sleep to mW active, and to support energy harvesting (EH) from multiple environmental sources. This article presents an adaptive and firmware-configurable power supply unit that enables intelligent devices to operate in the sub μW range while achieving self-sustainability through EH. The microcontroller-based design allows efficient conversion from batteries, dc, ac environmental sources, and nA quiescent currents. Source and load power points are decoupled with multiple dc–dc converters aiming to supply loads with adaptive voltage scaling and achieving high reliability. Experimental results show the flexibility and efficiency of this approach: the proposed power supply unit achieves a quiescent current of 54 nA and a maximum peak load current of 300 mA, delivered with an end-to-end power efficiency above 85%. [ABSTRACT FROM AUTHOR]

High-performance computing (HPC) processors are nowadays integrated cyber-physical systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To efficiently satisfy real-time multi-input multi-output (MIMO) optimal power requirements, high-end processors integrate an on-die power controller system (PCS). While traditional PCSs are based on a simple microcontroller (MCU)-class core, more scalable and flexible PCS architectures are required to support advanced MIMO control algorithms for managing the ever-increasing number of cores, power states, and process, voltage, and temperature variability. This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCS platform consisting of a single-core MCU with fast interrupt handling coupled with a scalable multi-core programmable cluster accelerator and a specialized DMA engine for the parallel acceleration of real-time power management policies. ControlPULP relies on FreeRTOS to schedule a reactive power control firmware (PCF) application layer. We demonstrate ControlPULP in a power management use-case targeting a next-generation 72-core HPC processor. We first show that the multi-core cluster accelerates the PCF, achieving 4.9x speedup compared to single-core execution, enabling more advanced power management algorithms within the control hyper-period at a shallow area overhead, about 0.1% the area of a modern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based, closed-loop emulation framework that leverages the heterogeneous SoCs paradigm, achieving DVFS tracking with a mean deviation within 3% the plant's thermal design power (TDP) against a software-equivalent model-in-the-loop approach. Finally, we show that the proposed PCF compares favorably with an industry-grade control algorithm under computational-intensive workloads. [ABSTRACT FROM AUTHOR]

Electroencephalography (EEG) is widely used to monitor epileptic seizures, and standard clinical practice consists of monitoring patients in dedicated epilepsy monitoring units via video surveillance and cumbersome EEG caps. Such a setting is not compatible with long-term tracking under typical living conditions, thereby motivating the development of unobtrusive wearable solutions. However, wearable EEG devices present the challenges of fewer channels, restricted computational capabilities, and lower signal-to-noise ratio. Moreover, artifacts presenting morphological similarities to seizures act as major noise sources and can be misinterpreted as seizures. This paper presents a combined seizure and artifacts detection framework targeting wearable EEG devices based on Gradient Boosted Trees. The seizure detector achieves nearly zero false alarms with average sensitivity values of 65.27 % for 182 seizures from the CHB-MIT dataset and 57.26 % for 25 seizures from the private dataset with no preliminary artifact detection or removal. The artifact detector achieves a state-of-the-art accuracy of 93.95 % (on the TUH-EEG Artifact Corpus dataset). Integrating artifact and seizure detection significantly reduces false alarms—up to 96 % compared to standalone seizure detection. Optimized for a Parallel Ultra-Low Power platform, these algorithms enable extended monitoring with a battery lifespan reaching 300 h. These findings highlight the benefits of integrating artifact detection in wearable epilepsy monitoring devices to limit the number of false positives. [ABSTRACT FROM AUTHOR]

Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a general-purpose, ultraefficient chiplet-based architecture for data-parallel FP workloads. We have manufactured a prototype of the chiplet’s computational core in Globalfoundries 22FDX process and demonstrate more than 5x improvement in energy efficiency on FP intensive workloads compared to CPUs and GPUs. The compute capability at high energy and area efficiency is provided in “Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads,” IEEE Trans. Comput., containing eight small integer cores, each controlling a large floating-point unit (FPU). The core supports two custom ISA extensions: The SSRs extension elides explicit load and store instructions by encoding them as register reads and writes (“Stream semantic registers: A lightweight RISC-V ISA extension achieving full compute utilization in single-issue cores,” IEEE Trans. Comput.). The floating-point repetition extension decouples the integer core from the FPU allowing floating-point instructions to be issued independently. These two extensions allow the single-issue core to minimize its instruction fetch bandwidth and saturate the instruction bandwidth of the FPU, achieving FPU utilization above 90%, with more than 40% of core area dedicated to the FPU. [ABSTRACT FROM AUTHOR]

Power and thermal management are critical components of high-performance-computing (HPC) systems, due to their high-power density and large total power consumption. The assessment of thermal dissipation by means of compact models directly from the thermal response of the final device enables more robust and precise thermal control strategies as well as automated diagnosis. However, when dealing with large-scale systems “in production,” the accuracy of learned thermal models depends on the dynamics of the power excitation, which depends also on the executed workload, and measurement nonidealities such as quantization. In this article we show that, using an advanced system identification algorithm, we are able to generate very accurate thermal models (average error lower than our sensors quantization step of 1 °C) for a large-scale HPC system on real workloads for very long time periods. However, we also show that: 1) not all real workloads allow for the identification of a good model and 2) starting from the theory of system identification it is very difficult to evaluate if a trace of data leads to a good estimated model. We then propose and validate a set of techniques based on machine learning and deep learning algorithms for the choice of data traces to be used for model identification. We also show that deep learning techniques are absolutely necessary to correctly choose such traces up to 96% of the times. [ABSTRACT FROM AUTHOR]

Thermal-aware design and online optimization of the cooling effort are becoming increasingly important in current and future high-performance computing (HPC) systems. A fundamental requirement to effectively develop such techniques is the availability of distributed and compact models representing the system thermal behavior. System identification algorithms allow to extract models directly from the thermal response of the target device. This article proposes a novel thermal identification approach for real, in-production HPC systems, which is capable of extracting thermal models from a computing node affected by quantization noise on the temperature measurements as well as operating in the free-cooling mode, with variable ambient temperature. The approach allows also to identify the physical floorplan of the CPU dies in supercomputing nodes. The effectiveness of the proposed methodology has been tested on a node of the CINECA Galileo Tier-1 supercomputer system. [ABSTRACT FROM AUTHOR]

Objective: We develop a fast learning algorithm combining symbolic dynamics and brain-inspired hyperdimensional computing for both seizure onset detection and identification of ictogenic (seizure generating) brain regions from intracranial electroencephalography (iEEG). Methods: Our algorithm first transforms iEEG time series from each electrode into symbolic local binary pattern codes, from which a holographic distributed representation of the brain state of interest is constructed across all the electrodes and over time in a hyperdimensional space. The representation is used to quickly learn from few seizures, detect their onset, and identify the spatial brain regions that generated them. Results: We assess our algorithm on our dataset that contains 99 short-time iEEG recordings from 16 drug-resistant epilepsy patients being implanted with 36–100 electrodes. For the majority of the patients (ten out of 16), our algorithm quickly learns from one or two seizures and perfectly (100%) generalizes on novel seizures using $k$ -fold cross-validation. For the remaining six patients, the algorithm requires three to six seizures for learning. Our algorithm surpasses the state-of-the-art including deep learning algorithms by achieving higher specificity (94.84% versus 94.77%) and macroaveraging accuracy (95.42% versus 94.96%), and 74× lower memory footprint, but slightly higher average latency in detection (15.9 s versus 14.7 s). Moreover, the algorithm can reliably identify (with a $p$ -value $< 0.01$) the relevant electrodes covering an ictogenic brain region at two levels of granularity: cerebral hemispheres and lobes. Conclusion and significance: Our algorithm provides: 1) a unified method for both learning and classification tasks with end-to-end binary operations; 2) one-shot learning from seizure examples; 3) linear computational scalability for increasing number of electrodes; and 4) generation of transparent codes that enables post-translational support for clinical decision making. Our source code and anonymized iEEG dataset are freely available at http://ieeg-swez.ethz.ch. [ABSTRACT FROM AUTHOR]

In recent years approximate computing has been extensively explored as a paradigm to design hardware and software solutions that save energy by trading off on the quality of the computed results. In applications that involve numerical computations with wide dynamic range, precision tuning of floating-point (FP) variables is a key knob to leverage the energy/quality tradeoff of program results. This aspect assumes maximum relevance in the transprecision computing scenario, where accuracy of data is tuned at fine grain in application code. Performing precision tuning at fine grain requires a software development flow that streamlines the assessment of which variables have “precision slack” within an application. In this paper, we introduce FlexFloat, an open-source software library that has been expressly designed to aid the development of transprecision applications. FlexFloat provides a C/C++ interface for supporting multiple FP formats. Unlike alternative libraries, FlexFloat enables to control the bit-width of mantissa and exponent fields and provides advanced features for the collection of runtime statistics, reducing the FP emulation time compared to the state-of-the-art solutions. Its design allows to emulate the behavior of standard IEEE FP types and custom extensions for reduced-precision computation. This makes the library suitable for adoption in multiple contexts, from manual exploration to integration into automatic tools. Experimental findings demonstrate that our approach can be used to perform a complete precision analysis from which deriving multiple program versions depending on the energy/quality tradeoff. Furthermore, we show that the adoption of our methodology can lead to a significant reduction of energy consumption even on current commercial hardware (an embedded GPGPU). [ABSTRACT FROM AUTHOR]

Minimizing the power consumption of always-on sensors is crucial for extending the lifetime of battery-operated devices that are required to monitor events continuously and for long periods. This paper proposes a novel programmable $\mu \text{W}$ event-driven acoustic detector featuring “always-on” audio pattern recognition. The event-driven detector detects up to eight programmable spectral–temporal features extracted with a low-power single-channel analog circuit and classifies the features by an onboard microcontroller. The event-driven detector is combined with novel microbial fuel cells (MFCs) to achieve self-sustainability in an underwater scenario. Experimental results demonstrate that the power consumption of the detector is only $26.89~\mu \text{W}$ during always-on mode, achieving up to 59-dB sound pressure level of sensitivity. High detection accuracy of up to 95.89% in recognizing acoustic patterns has been experimentally verified. Accurate measurements with commercial MFCs demonstrate the capability to achieve self-sustainability in always-on monitoring. [ABSTRACT FROM AUTHOR]

A key enabler for the ever-increasing adoption of FPGA accelerators is the availability of frameworks allowing for the seamless coupling to general-purpose host processors. Embedded FPGA+CPU systems still heavily rely on copy-based host-to-accelerator communication, which complicates application development. In this paper, we present a hardware/software framework for enabling transparent, shared virtual memory for FPGA accelerators in embedded SoCs. It can use a hard-macro IOMMU if available, or a configurable soft-core IOMMU that we provide. We explore different TLB configurations and provide a comparison with other designs for shared virtual memory to gain insight on performance-critical IOMMU components. Experimental results using pointer-rich benchmarks show that our framework not only simplifies FPGA-accelerated application development, it also achieves up to 13x speedup compared to traditional copy-based offloading. [ABSTRACT FROM AUTHOR]