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The semiconductor manufacturing is one of the most sophisticated processes in modern industries. It contains hundreds of complex operations, and this makes semiconductor reliability a challenging task especially in recent years that integrated circuits (ICs) have been broadly used at much wider areas including the health cares, automotive, and aerospace applications, where safety is the major concern. To make things worse, due to the shorter product life cycles and severe competitions, time-consuming reliability tests become unacceptable. The industries are in urgent need of a fast and effective way to quickly assess reliability risks. Under all these stringent limitations and the high reliability targets, we propose a consolidated approach that consists of an efficient and effective reliability baseline (BL) management system and a test scheme developed based on sequential probability ratio test (SPRT). To ensure a trustworthy setting for the SPRT test scheme, we apply the Bayesian approach to continuously update the BL database. An integrated flow chart is introduced to elucidate our proposed methodology. It is the first time SPRT is applied on reliability risk assessments with two unknown parameters. Several actual cases from semiconductor arena are reported to demonstrate the merits and powers of our proposed methodology. From these real cases, as a side benefit, we show the wide applicability of our method, which does not limit to reliability but on yield and functionality checks as well. To facilitate the use of our method by field practitioners, we do the best to explain derivations in a plain manner and provide analysis codes in R (in Supplementary Material) to make our approach as portable as possible. [ABSTRACT FROM AUTHOR]

The ultra-low k dielectrics have been widely used as semiconductor technology steps into 45 nm, 28 nm, and more advanced nodes. Combined with the rapid shrinks of critical dimensions, the ultra-low k dielectrics face challenges to retain the benefits of interconnect scaling both on their manufacturability and reliability performances. In this paper, abnormal failure phenomena were investigated on 28 nm ILD (Intra Level Dielectric) and IMD (Inter Metal Dielectric) qualifications and 40 nm mass production. A new failure mechanism of metal 1 to poly (M1-to-poly) leaky path was proposed based on theoretical investigations and experiments. Based on our newly proposed dielectric breakdown mechanism, a series of innovative test structures were designed for early detections and evaluations of reliability performances. These newly designed test structures have been proven to be useful due to better representing actual using profiles, more precise reliability evaluations, and more effective monitors on process variations at mass production. [ABSTRACT FROM AUTHOR]

The effects of baking temperature on back-end-of-line (BEOL) reliability were explored on 28 nm technology node. We found that stress migration (SM) worse temperature showed up around 200 °C and apparent negative resistance (R) shifts appeared after baking at high temperatures. The Electromigration (EM) performance behaved the temperature dependence and the high baking temperature improved the main time-to-failure (TTF) distribution. Interlayer dielectric (ILD) time dependence dielectric breakdown (TDDB) performance was enhanced at low baking temperatures. [ABSTRACT FROM AUTHOR]

With technologies scaling down to 28 nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO 2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times. [ABSTRACT FROM AUTHOR]

The NBTI (negative bias temperature instability) performance of 28 nm HfO 2 -based HKMG (high-κ metal gate) I/O thick oxide p-MOSFETs with different I/O oxide processes is reported. The results show that the NBTI performance from ISSG (in-situ steam generation) process is better than that from the furnace Gox1 process. The NBTI dependence on the PDA (post deposition anneal) process is studied and we show that PDA can significantly improve NBTI. We investigate the influence of DPN (decoupled plasma nitridation) on NBTI; the NBTI performance from the DPN process is much better than that from non-DPN processes for the devices with the same EOT (electrical oxide thickness). Based on the experiments, we propose an extended NBTI model, which incorporates nitrogen concentration in the formula for the process with DPN. This extension provides much clearer direction on process tuning to better control the DPN dosage and the EOT to meet both process electric and reliability requirements. [ABSTRACT FROM AUTHOR]

In this paper, we report electromigration (EM) reliability optimizations using highly efficient uniform design (UD). Considering the large error that results from using a single lifetime index, and the different EM failure modes, we introduce a new proportion index incorporating early failures to compensate for the shortage of using a single traditional intrinsic lifetime index in our Design of Experiments (DOE). Applying a supersaturated UD DOE, we greatly reduce (> 70\\% savings) the number of wafers used in experiments, comparing to the classical RSM design. This very economic experiment has successfully maximized EM lifetimes, which are more than 10 times longer, and without early failure, in a much shorter period of time. [ABSTRACT FROM PUBLISHER]

Yield and reliability susceptibility would become obvious with the increase in the complexity of manufacturing technology. Yield and reliability enhancement is always our pursuit. However, tradeoffs between yield and reliability, or between Fab and assembly house, are often observed during the technology development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new technology, some practical experiences on solving tradeoffs in semiconductor manufacturing are reported; a generic procedure to handle the tradeoff problem is proposed, and the effectiveness was also proved. Early detection capability, baseline knowledge management, fully understanding customers' requirements, and effectively consolidating all parties' efforts are considered to play key roles in the procedure. It is believed that such a procedure can be also applied to solve the tradeoff problem in other industries. [ABSTRACT FROM AUTHOR]

A method is proposed in this paper to determine whether a product, a component, or a system in reliability life testing has a longer lifetime than the other. We propose two indices to compare reliability. The comparison is also distribution-free; i.e., it does not require the assumption on the lifetime distributions. A comparability index that is derived by integrating the weighted difference between the reliability functions of the two groups under comparison is named the "Better or Worse" (BOW) index. The second comparability index that is derived by calculating the overlapping area under the two distributions in comparison is named "Reliability Comparability" (RC) to quantify the degree of similarity between the two distributions. These two new indices are compared with the conventional methods currently used in the IC industries. Practical applications in lifetime-type reliability comparison are also illustrated in this paper. [ABSTRACT FROM AUTHOR]

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions. [Copyright &y& Elsevier]

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH4) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes. [Copyright &y& Elsevier]

Proposes a nonparametric approach to estimate the optimal system burn-in time in semiconductor manufacturing. Elimination of residual defects; Incompatibility in different subsystems and at the system level; Disadvantages of performing system burn-in; Checking of the constant failure rate.

Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which will result in misidentification. In this paper, a novel deep learning model called adaptive balancing generative adversarial network (AdaBalGAN) is proposed for the defective pattern recognition (DPR) of wafer maps with imbalanced data. In addition, a categorical generative adversarial network is improved to generate simulated wafer maps in high fidelity and classify the patterns with high accuracy for all defective categories. Taking consideration of the various learning abilities of the DPR model for different patterns into account, an adaptive generative controller is designed to balance the number of samples of each defective type according to the classification accuracy. The experiment results indicated that the proposed AdaBalGAN model outperforms conventional models with higher accuracy and stability for the DPR of wafer maps. Further results of comparative experiments revealed that the proposed adaptive generative mechanism can enhance and balance the recognition accuracy for all categories in the DPR of wafer maps. [ABSTRACT FROM AUTHOR]

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations. [ABSTRACT FROM AUTHOR]