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Summary: A multiplier, as a key component in many different applications, is a time‐consuming, energy‐intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping computation quality satisfactory. A novel multicolumn 3,3:2 inexact compressor is presented in this paper. It takes three partial products from two adjacent columns each for rapid partial product reduction. The proposed inexact compressor and its derivatives enable us to design a high‐speed approximate multiplier. Then, another ultra‐fast, high‐efficient approximate multiplier is achieved by utilizing a systematic truncation strategy. The proposed multipliers accumulate partial products in only two stages, one fewer stage than other approximate multipliers in the literature. Implementation results by the Synopsys Design Compiler and 45 nm technology node demonstrate nearly 11.11% higher speed for the second proposed design over the fastest existing approximate multiplier. Furthermore, the new approximate multipliers are applied to the image processing application of image sharpening, and their performance in this application is highly satisfactory. It is shown in this paper that the error pattern of an approximate multiplier, in addition to the mean error distance and error rate, has a direct effect on the outcomes of the image processing application. [ABSTRACT FROM AUTHOR]

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard. • Deploying dynamic logic (DL) in the design of approximate full adders for the first time. • Designing ultra-low area and energy consumption full adder structures. • Applying the proposed adders in the image processing application. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is a computational paradigm that is based on encoding information in terms of the configuration of charge among quantum dots without requiring current switches. Mostly, QCA cells have been realized by employing the electron switching in square quantum-dot cells. In this paper, a triangular metal-dot cell with a single electron is proposed to represent ternary information. Then, an inverter chain of the proposed triangle cells is suggested through juxtaposing the cells. Additionally, wire crossing and wire fan-out are the two inseparable subjects of QCA wire. A wire-crossing method is presented for the proposed ternary wire. Wire fan-out is also dealt with in this paper by an innovative approach. The correctness of operation of proposed cells and wires are thoroughly verified by applying the physical relations. [ABSTRACT FROM AUTHOR]

Purpose: Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology. Design/methodology/approach: The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations. Findings: The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved. Originality/value: These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare. [ABSTRACT FROM AUTHOR]

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied. [ABSTRACT FROM AUTHOR]

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM . In addition, simulation results by HSPICE and 32 nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one ( CCW CYCLE ). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW . [ABSTRACT FROM AUTHOR]

This paper deals with the bridge-style circuits. They are highly efficient in terms of transistor density per unit of area. They comply with the conventional CMOS style and form a full-swing and robust structure. First, we clarify the necessary conditions under which a Boolean function can be implemented fully symmetrical. Then, it is demonstrated that it is possible to design out of functions fully symmetrical. Eventually, we show how the pull-up and pull-down networks are constructed in a bridge circuit for any three-input function which fulfils the conditions of being implemented fully symmetrical. [ABSTRACT FROM AUTHOR]

Novel designs of current-mode Ternary minimum (AND) and maximum (OR) are proposed in this paper based on Carbon NanoTube Field Effect Transistors (CNTFET). First, these Ternary operators are designed separately. Then, they are combined together in order to generate both outputs concurrently in an integrated design. This integration results in the elimination of common parts when both functions are required at the same time. The third proposed current-mode integrated circuit generates both ternary operators with the usage of only 30 transistors. The new designs are composed of three main parts: (1) the part which converts current to voltage; (2) threshold detectors; and (3) the parallel paths through which the output current flows. Unlike the previously presented structure, there is no need for any constant current source within the new designs. This elimination leads to less static power dissipation. The second proposed current-mode segregated Ternary minimum operates 43% faster and consumes 40% less power in comparison with a previously presented structure. [ABSTRACT FROM AUTHOR]

Abstract: Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis. [Copyright &y& Elsevier]

This paper presents a quaternary latch and two edge-sensitive quaternary flip-flops (QFFs), which are capable of storing a quaternary digit. Two complementary outputs are often generated in a flip-flop inevitably. However, the new designs offer the opportunity to eliminate one of the quaternary outputs with the aim of area and static power reduction. This feature reduces the number of transistors by four and cuts static power dissipation by 47.5% when resistive voltage dividers are used. Simulation results show promising outcomes for the proposed QFFs, which are based on CMOS technology and a single power supply. They provide an excellent compromise between the delay and power factors in comparison with the previous CMOS and CNFET QFFs. The first proposed design with resistive voltage dividers, Design #1, operates with 70.96% and 38.19% lower power-delay product (PDP) than the earlier QFFs with the fastest speed and the lowest power consumption, respectively. The second one with capacitive voltage dividers, Design #2, avoids continuous static current during the production of logic values '1' and '2' and improves PDP even more significantly. Setup time, hold time, critical clock skew, and robustness against process, voltage, and temperature (PVT) variations are also measured showing considerable improvements compared to the previous designs. Finally, the applicability and correct functionality of the proposed QFFs in larger sequential circuits is verified by designing a quaternary shift register and a quaternary decrementing counter. [ABSTRACT FROM AUTHOR]

In this paper, novel configurations of a quaternary edge-sensitive flip-flop are introduced. They are realized by employing carbon nanotube field-effect transistors (CNTFETs). The first structure is based on a tri-state quaternary buffer integrated into a multiplexer. In the second proposed design, a quaternary input is decoded and then stored by tri-state binary buffers. In the end, binary values are converted to a quaternary value again. Finally, the last proposed circuit is not a d-type flip-flop; instead, a quaternary value is loaded by two controlling signals. The innovative configurations reduce the number of transistors, power consumption, and delay compared to previous approaches. The proposed designs are simulated and tested using HSPICE software and the CNTFET 32 nm library. The simulation results exhibit promising performance for the given quaternary flip-flops. For example, while having eight fewer transistors, the first proposed design has 87.7% higher performance in terms of power-delay product compared to one of the competitors with a similar structure. Finally, a quaternary shift register and a quaternary counter are also implemented to demonstrate the applicability of the third proposed quaternary FF in larger sequential circuits. [ABSTRACT FROM AUTHOR]

Purpose: The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors. Design/methodology/approach: Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image. Findings: Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder. Originality/value: Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time. [ABSTRACT FROM AUTHOR]