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Practical applications of high-temperature superconductors will be governed by their current transport and mechanical characteristics. With careful control of the processing parameters high-quality long-length mono- and multifilament Bi-2223 conductors have been fabricated by the powder-in-tube technique. A critical current density (J/sub c/) of up to 1.2/spl times/10/sup 4/ A cm/sup -2/ has been observed at 77 K in a 1260-m-long multifilament conductor containing 37 monocore filaments. A high-temperature superconducting magnet and a prototype transformer were fabricated and characterized from such long-length conductors. Extensive studies on the in-situ strain characteristics of the mono- and multifilament conductors have been conducted. Multilayer silver/superconductor composite tapes, fabricated by a novel chemical etching technique, were also observed to exhibit improved strain tolerance characteristics. To further improve the current characteristics of the Bi-2223 tapes the wire-in-tube technique was adopted. A J/sub c/ value >10/sup 5/ A cm/sup -2/ at 77 K and in self field have been obtained in a Bi-2223 tape fabricated by the wire-in-tube method. [ABSTRACT FROM PUBLISHER]

Abstract: For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs. [Copyright &y& Elsevier]

Abstract: Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the improvement of the off-state leakage current (I off), which was mainly attributed to the decreased perimeter component of the gate leakage current (I G) particularly, at the low field region. The better electrical characteristics are due to the low trap density at the edge of gate oxides in the S/D region of CMOSFETs. [Copyright &y& Elsevier]

Abstract: Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs. [Copyright &y& Elsevier]

Abstract: The evolution over time of the leakage current in HfO2-based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS. [Copyright &y& Elsevier]

We report on terahertz detection (from 0.2 THz to 2.4 THz) by Si FinFETs of different widths (with 2, 20, and 200 fins connected in parallel). FinFETs (with a small number of fins and with feature sizes as short as 20 nm to 40 nm) showed a very high responsivity (far above that previously measured for standard CMOS). We explain this improvement by negligible narrow channel effects. [ABSTRACT FROM AUTHOR]

An attempt is made to correlate electrical measurement results to specific defects in the dielectric stacks of high-k/metal gate devices. Defect characteristics extracted from electrical data were compared to those obtained by ab initio calculations of the dielectric structures. It is demonstrated that oxygen vacancies in a variety of charge states and configurations in the interfacial SiO2 layer of the high-k gate stacks contribute to random telegraph noise signal, time-dependent dielectric breakdown, and the flatband voltage roll-off phenomenon. [ABSTRACT FROM AUTHOR]

The article provides information on metal oxide semiconductor field-effect transistors (MOSFETs). It shows that an analysis of the noise measurements allows the extraction of electron trap characteristics. It states the use of balance equation to facilitate conventional random telegraph signal (RTS) analysis. It also discusses the importance of the structural relaxation process. Results show that the charge exchange process helps identify the defects responsible for low frequency noise.

Abstract: The influence of substrate heterostructure (Si/ SiGe/ Si) on performance of MOSFETs with high-k/metal gate stacks has been studied. In particular, the effects of the channel thickness on the performance and short channel properties are evaluated. It is found that these heterostructures, when designed optimally, can not only exhibit high mobility but also excellent control of short channel effects down to 70 nm gate length. [Copyright &y& Elsevier]

Schottky barrier height tuning using high-κ/SiO2 interfacial dipoles is reported. Schottky barrier heights of 1.0 and 0.2 eV are observed in a TaN/p-Si diode by insertion of thin layers of high-κ (LaOx,AlOx) and SiO2 at the metal-semiconductor interface. The dipole tunes the effective work function of TaN/p-Si by more than 0.8 eV to achieve effective Schottky barrier heights near conduction and valence band edge. LaOx (n-type) and AlOx (p-type) have a dipole potential offsets estimated to be 0.3 and 0.5 V, respectively. Applications to lowering contact resistivity are discussed, as well as a comparison of other dipole offsets. [ABSTRACT FROM AUTHOR]

Quadratic voltage coefficient of capacitance (VCC) for ZrO2–SiO2 multilayered dielectric metal-insulator-metal capacitors depends strongly on the stacking sequence of the layered dielectrics. The quadratic VCC of an optimized SiO2/ZrO2/SiO2 stack and ZrO2/SiO2/ZrO2 stack were +42 and -1094 ppm/V2, respectively, despite the same total SiO2 and ZrO2 dielectric thickness in the stack. The observed difference in quadratic VCC depending on dielectric stacking sequence is explained by taking into account both the interface and bulk dielectric responses to the applied voltage. [ABSTRACT FROM AUTHOR]

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si/SiOx/HfSiON/REOx/metal gated nFETs as follows: Sr

The article discusses the advancements of the strain-enhanced scaling of high-k(high dielectric constant) and metal gate (HK+MG) Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET). These advancements have allowed improvements in gate control owing to the aggressive scaling of equivalent oxide thickness (EOT), which has not been possible with conventional silicon dioxide (SiO) or poly-gate technology.

Rare earth (RE) doping (Gd, Er, Dy) of HfO2 reduces leakage current by three orders of magnitude compared with pure HfO2. The key to reducing HfO2 leakage current and equivalent oxide thickness (EOT) is stabilization of the higher permittivity tetragonal phase. RE doping of 10–20 at. % stabilizes tetragonal HfO2 and increases permittivity. The maximum permittivity achieved for HfREOx is 28. The maximum permittivity for ZrREO is 32. HfGdO metal-insulator-semiconductor capacitors with EOT=1.93 nm and leakage current <1×10-8 A/cm2 after 1070 °C have been demonstrated. [ABSTRACT FROM AUTHOR]

A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function. [ABSTRACT FROM AUTHOR]

It is shown that the work function of Ta1-xAlxNy depends on the electrode and gate dielectric compositions. Specifically, the work function of Ta1-xAlxNy increased with SiO2 content in the gate dielectric, reaching as high as 5.0 eV on SiO2; the work function was nearly 400 mV smaller on HfO2. In addition, the work function decreased with increasing nitrogen content in the Ta1-xAlxNy metal gate. Increasing Al concentration increased the work function up to about 15% Al, but the work function decreased for higher Al concentrations. Chemical analysis shows that Al–O bonding at the interface correlates with the observed work function values. [ABSTRACT FROM AUTHOR]