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Two algorithms, both based around multiplication, one defined by Andrew Donald Booth in 1950 and the other defined by Anatoly Alexeevitch Karatsuba in 1960 can be applied to other types of operations. We know from recent results that to perform some algebraic transformations it is more efficient to calculate an inverse effect of a smaller magnitude together with an original action with a higher rank, than the initial operation, reaching the final element with less transitions. In this paper, we present an addition algorithm on |$\mathbb {Z}/m\mathbb {Z}$| of big-integer numbers based on these concepts, using an alternative to traditional hardware implementation for binary addition based on FULL-ADDER cells, allowing the reduction of space complexity compared with other techniques, such as carry-lookahead, letting us calculate a modular addition in an optimal order complexity of |$\mathcal {O}(n)$| without adding more complexity due to reduction operations. [ABSTRACT FROM AUTHOR]

Modular multiplication is the most crucial operation in many public-key crypto-systems, which can be accomplished by integer multiplication followed by a reduction scheme. The reduction scheme involves a division operation that is costly in terms of computation time and resource consumption both on hardware and software platforms. Montgomery modular multiplication is widely used to eliminate the costly division operation. This work presents an efficient implementation of full-word Montgomery modular multiplication. This incorporates the more efficient Karatsuba algorithm where the complexity of multiplication is reduced form O ( n 2 ) to O ( n 1.58 ) . The Karatsuba algorithm recommends to split the operands into smaller chunks. Two methods of operand splitting are exploited: (1) Four Parts (FP) splitting and (2) Deep Four Parts (DFP) splitting. These methods are then used in the design of Integer Multiplier (IM) and Montgomery Multiplier (MM). The design is synthesized using Xilinx ISE 14.1 Design Suite for Virtex-5, Virtex-6 and Virtex-7. Compared with the traditional implementations, the proposed scheme outperforms all other designs in terms of throughput and area-delay product. Moreover, the proposed scheme utilizes the least hardware resources in the known literature. The proposed MM design is able to compute modular multiplication for the Elliptic Curve Cryptography (ECC) field sizes of 192–512 bits. [ABSTRACT FROM AUTHOR]

In Internet of Things (IoT), sensor devices should deliver the collected sensor data to the server after the data is encrypted. The encrypted data cannot be eavesdropped by adversaries but the side channel information including clock cycles and power consumption patterns during encryption operations can leak the secret information. For this reason, cryptography engineering should prevent potential threats by designing the cryptography functions in secure manner. In this paper, we explore the feasible side channel attacks on cryptography operations, particularly polynomial multiplication for Galois/Counter Mode of operation (GCM). We perform the horizontal Correlation Power Analysis (CPA) on the most well-known Lopez et al.’s polynomial multiplication and successfully extract the secret values from power consumption patterns. In order to prevent proposed attack model, we suggest a masked polynomial multiplication, ensuring a regular and constant-time solution without potential vulnerabilities including Look-up Table (LUT) access and branch statements. With proposed polynomial multiplication, we suggest the secure and efficient implementation of GCM on the low-end embedded processor. Finally, we further explore the long polynomial multiplication for Elliptic Curve Cryptography (ECC) operations. We exploit the combination of Karatsuba algorithm and proposed masked polynomial multiplication, which achieved the practically fast polynomial multiplication on embedded processors. [ABSTRACT FROM AUTHOR]

Most of the public key cryptography algorithms require efficient big integer multiplications. In this paper, we show how to develop efficient integer multiplication algorithms for cryptographic applications by combining different methods. We determine the complexities by taking into account the cost of single word multiplication, single word addition and double word addition on different platforms. This paper is an extended version of [11]. We add the complexity of the last term method that is used for computing complexity of multiplication of degree n -- 1 polynomials from the product of degree n -- 2 polynomials. The unbalanced refined Karatsuba 2-way multiplication algorithm is also included. These new contributions improved the complexity results introduced in [11]. Moreover, we present the best multiplication algorithm complexities for NIST primes on different implementation platforms. [ABSTRACT FROM AUTHOR]

We present a new type of bit-parallel non-recursive Karatsuba multiplier over $GF(2^m)$ generated by an arbitrary irreducible trinomial. This design effectively exploits Mastrovito approach and shifted polynomial basis (SPB) to reduce the time complexity and Karatsuba algorithm to reduce its space complexity. We show that this type of multiplier is only one $T_X$ slower than the fastest bit-parallel multiplier for all trinomials, where $T_X$ is the delay of one 2-input XOR gate. Meanwhile, its space complexity is roughly 3/4 of those multipliers. To the best of our knowledge, it is the first time that our scheme has reached such a time delay bound. This result outperforms previously proposed non-recursive Karatsuba multipliers. [ABSTRACT FROM PUBLISHER]

In this study, an area and power‐efficient iterative floating‐point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single‐precision (SP) and double‐precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look‐up tables (LUTs), and 31.2% less flip‐flops while having 4% faster clock frequency on Virtex‐5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower‐power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex‐7 and Altera Arria‐10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM‐90 nm ASIC platform are reported. [ABSTRACT FROM AUTHOR]

Multidigit multiplication is widely used for various applications in recent years, including numerical calculation, chaos arithmetic, and primality testing. Systems with high performance and low energy consumption are demanded, especially for image processing and communications with cryptography using chaos. Karatsuba algorithm with computational complexity of O(n1.58) has been employed in software for multiplication of hundreds to thousands of bits, where n stands for bit-length of operands. In this paper, hardware design of multidigit integer multiplication based on Karatsuba algorithm is described and its VLSI realization is evaluated in terms of the cost, performance, and energy consumption. We present two design choices of the Karatsuba hardware: RKM (Recursive Karatsuba Multiplier) and IKM (Iterative Karatsuba Multiplier). We found that RKM has less area cost than WTM (Wallace Tree Multiplier) for bit-length larger than 29 with area cost of 30mm2. Critical path delay of RKM is always larger than that of WTM. Therefore, we should use WTM as combinational circuits for IKM to have better cost performance. We also found that a version of IKM using 0.18µm process can perform 1024-bit multiplications 30 times faster than software at the area cost of 10.9mm2. Energy for the computation by the IKM version was found to be nearly 1/600 of that consumed by general-purpose processor which executes the software. The results obtained by this study will help system designers for applications requiring multidigit multiplication to select design alternatives including ASIC realization. © Wiley Periodicals, Inc. Electron Comm Jpn, 92(4): 9–20, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecj.10086 [ABSTRACT FROM AUTHOR]

In this comment, we show that the gate complexity of Karatsuba polynomial multipliers presented in the above paper can be reduced by exploring the common subexpressions. [ABSTRACT FROM AUTHOR]

We show that multiplication complexities of n-term Karatsuba-Like formulae of GF(2)[x] (7 < n < 19) presented in the above paper can be further improved using the Chinese Remainder Theorem and the Construction multiplication modulo (x -∞)w. [ABSTRACT FROM AUTHOR]

It is well known that Chinese Remainder Theorem (CRT) can be used to construct efficient algorithms for multiplication of polynomials over GF(2). In this note, we show how to select an appropriate set of modulus polynomials to obtain minimal number of multiplications. [ABSTRACT FROM AUTHOR]