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Power dissipation of CMOS integrated circuits continues to increase as a result of device scaling. In this paper circuit design techniques for high-speed low-power CMOS VLSIs for multimedia applications are reviewed. In addition to general guidelines for low-power design and a summary of recent research, we discuss in detail some of the recent research achievements including low-voltage circuits such as MTCMOS and VTCMOS, and low-capacitance circuits such as pass-transistor logic circuits. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(9): 67–74, 1998 [ABSTRACT FROM AUTHOR]

The rapid performance progress in processors and memory cores by technology scaling requires further improvement in interface bandwidth. However, interface bandwidth is not keeping up with the processing speed of the core and is becoming a bottleneck in system performance. To fill the performance gap, wideband lowpower low-cost interfaces are strongly demanded. A wireless proximity interface that uses inductive coupling is one such interface expected to be used for interchip links in high-performance 3D system integration. Inductive coupling interfaces use the magnetic near-field induced by micro-coils. The coils (channels) can be arranged in a dense array because magnetic near-field localizes in the proximity of each coil, and crosstalk between the channels is small. Therefore, inductive coupling interfaces are suitable for wideband low-cost proximity communication. An inductive coupling interface can also realize highly reliable communication with low power consumption. Evaluation systems developed to study the performance of inductive coupling interfaces have demonstrated the feasibility of the interfaces in a wide range of applications. [ABSTRACT FROM PUBLISHER]

H2 and NH3 detection with low power consumption was demonstrated by integrated chemiresistive Pt and PtRh nanosheet sensors on glass substrates. The self-heating effects realized low power and local heating of metal nanosheet sensors, enabling the integration of sensors with different operating temperatures. Based on different resistance changes in Pt and PtRh nanosheets toward H2 and NH3, the concentration of each gas was detected from a gas mixture by consuming around 1-mW power. For decreasing the power consumption and further integration of sensors, sensor scaling and pulsed operations were numerically and experimentally studied. In addition to good connectivity of metal nanosheet sensors to large-scale integration (LSI) circuits, improvements of the power consumption by sensor scaling were proven. The pulsed operations required for integrated sensor arrays maintained a sensor response, or a resistance change, of approximately 60%, even when the power consumption was reduced by 20%. [ABSTRACT FROM AUTHOR]

A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips. [ABSTRACT FROM PUBLISHER]

The authors developed a scalable heterogeneous multicore processor. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multicore accelerators enables various trade-offs between performance and energy consumption. The stacked chips interconnect through a scalable 3D network on a chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. No design change is needed, and hence, no additional nonrecurring engineering (NRE) cost is required. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. The authors developed a prototype system called Cube-1 with 65-nm CMOS test chips, and confirmed successful system operations, including 10 hours of continuous Linux OS operation. Simple filters and a streaming application were implemented on Cube-1 and performance acceleration up to about three times was achieved. [ABSTRACT FROM PUBLISHER]

The article describes a proposal for a low power recognition processor for multi-object parallel recognition of a versatile recognition processor (VRP) that employs AdaBoost algorithm--with Haar-like features (HF) and cascading classifier (CC) framework. A four-engineer team from Keio University of Yoko, Kanagawa, Yokohama, Japan developed three techniques in HF and CC implementation, namely, a classifier data cache (CDC) for CC, an HF coordinates decoder (HFCD) and an HF value extractor (HFVE). It also notes that the proposed processor offers eight times better power efficiency than conventional processors, with power consumption as low as 0.15 microwatts per frames per second (FPS) at 0.9 volts in a 90-nanometer (nm) complimentary metal-oxide-semiconductor (CMOS).