1. A 1- $\mu$ s Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration.
- Author
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Levski, Deyan, Wany, Martin, and Choubey, Bhaskar
- Subjects
- *
TIME-digital conversion , *CALIBRATION , *IMAGE sensors - Abstract
This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of <2 adding redundancy and providing ability for gain calibration using a per-column digital multiplication operation. The presented digital feedback correction scheme is applied online and in-column after the end of each conversion, occupying less than 5% of the ramp time. The architecture is verified on a $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion. [ABSTRACT FROM AUTHOR]
- Published
- 2019
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