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This work presents a hybrid column-parallel time-to-digital-converter interpolated (TDC) single-slope (SS) ADC with a digital delay element feedback. The proposed scheme solves the multiphase clock period matching problem in flash TDC-interpolation of SS ADCs without the use of a delay-locked-loop. The architecture employs open-loop delay elements for multiphase clock generation forming a lowered TDC radix of <2 adding redundancy and providing ability for gain calibration using a per-column digital multiplication operation. The presented digital feedback correction scheme is applied online and in-column after the end of each conversion, occupying less than 5% of the ramp time. The architecture is verified on a $1024\times128$ linescan image sensor testchip manufactured in a 0.13- $\mu \text{m}$ 1P3M CMOS process. The ADC operates at 250 MHz and achieves a 1- $\mu \text{s}$ ramp time and 4.4- $\mu \text{s}$ digital correlated double sampling row time for a 12-bit linear A/D conversion. [ABSTRACT FROM AUTHOR]

Noise analysis of the ramp reference voltage and its projection at the output of a conventional single-slope ramp analog-to-digital converter (ADC) is presented. This paper gives insight on the reference voltage noise origins during the continuous-time ramping phase of column-parallel CMOS image sensor ADCs, as well as its effect on the final ADC output noise. Theoretical modeling of an occurring random walk noise on continuous-time-based ramp references is presented first. Noise on the ramp does not directly add to the output noise of the ADC, but it is modulated and projected subject to given ramp rise time conditions. Test measurements show that the signal-dependent output noise is consistent with the rate of noise increase by the proposed random walk noise model. [ABSTRACT FROM AUTHOR]