Search

This study presents the first monolithically integrated full-duplex front-end for K/Ka satellite communication phased arrays. A 0.25 µm SiGe:C BiCMOS process was used to develop the integrated circuit. The receive and transmit channels are united into a common port through a novel duplexer. For each RF channel, the bias currents, the active channels and the power amplifier operation mode can be controlled through a serial bus. Amplitude and phase control are provided with fine granularity (65,536 states). In transmit mode, each channel provides 37.3 dB of gain with 12.9 dBm output power at 1-dB compression. In receive mode, 33.7 dB gain is measured with a noise figure of 3.2 dB. The amplitude/phase root-mean-square errors within the transmit (29.5-30.8 GHz) and receive (19.7-21 GHz) bands are below 0.7 dB/6.4° and 0.26 dB/1.1°, respectively. The chip occupies 1.64 × 3.5mm2 and it consumes 81 and 15.5 mW per transmit and receive channels, respectively. The use of a Doherty power amplifier with a novel dynamic adaptive bias circuit led to a 31% reduction of the total dc array power consumption. [ABSTRACT FROM AUTHOR]