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This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]

The recent SARS-CoV2 pandemic has put a great challenge on university courses. Electronics teaching requires real laboratory experiences for students, which cannot be realized if access to physical infrastructures is prohibited. A possible solution would be to distribute to students, at home, electronics equipment suitable for laboratory experiments, but no reasonable product is currently available off-the-shelf. In this paper, the design and development of a very-low-cost experimental board tailored to these needs is presented. It contains both programmable prototyping circuitry based on a microcontroller and an FPGA and a set of measurement instruments, similar to the ones found on a typical lab desk, such as a digital storage oscilloscope, multimeter, analog signal generator, logic state analyzer and digital pattern generator. A first board, suitable for analog and digital electronics experiments, has been designed and manufactured, and is described in this paper. The board has been successfully used in master's degrees and PhD courses. [ABSTRACT FROM AUTHOR]

This paper proposes a flexible and efficient implementation of the 2D $N$ -point discrete cosine transform (DCT) for the High Efficiency Video Coding (HEVC) standard. The DCT is implemented through the Walsh–Hadamard transform (WHT) followed by Givens rotations. This scheme is exploited to derive an adaptive algorithm, which allows computing of four different approximations ranging from the complete DCT to the WHT, by selectively skipping some rotations. This paper shows the statistical analysis of the DCT usage and derives a precomputation mechanism to adaptively skip rotations. Each approximation, referred to as a operating mode, is characterized by a large saving of operations, at the expense of very small quality loss. Then, two 2D-DCT architectures are proposed: the first one is totally unfolded, while the second one is folded. The two designs are finally synthesized with a 90-nm standard-cell library for a clock frequency of 250 MHz. Both architectures support real-time processing of 8K UHD video sequences at 64 and 26 fps, respectively, and show higher throughput and lower gate count compared with the state-of-art implementations. Moreover, power saving ranging from 28% to 56% can be achieved by working within the proposed operating modes. [ABSTRACT FROM PUBLISHER]

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network-on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based design. [ABSTRACT FROM AUTHOR]

Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, n-input \max^\ast approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of n data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., 10^-5, assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity. [ABSTRACT FROM PUBLISHER]

In this paper, we deal with practical implementation issues of the \max^ \ast operation in generalized form used for decoding of both turbo and low-density-parity-check (LDPC) codes. In particular, first, a unified framework for the so-called generalized \max^\ast operation is established, which includes most of the previously published algorithms already known for turbo decoding. Next, the hardware architectures used for the practical implementation of the generalized \max^\ast operation, which is derived from this novel framework, are revealed for the first time and further analyzed, in terms of hardware complexity reduction. It is also shown how this generalized \max^\ast operation can be adopted in LDPC decoding, achieving essentially optimal bit error rate performance with small computational complexity against other algorithms in joint turbo–LDPC architectures. This solution is useful in applications where joint decoding architectures are deployed to decode both turbo and LDPC codes. An important example of such application is in software radio receivers of 4G wireless communication systems, such as those proposed in conjunction with the WiMAX standard. [ABSTRACT FROM PUBLISHER]

The article discusses the use of coded communication between a couple of wireless sensor devices to reduce the transmission of dissipated energy with respect to uncoded communication. It explores the application of Different Low Density Parity Check (LDPC) codes in the method. It also shows the post layout results for a low-area low-energy detector.

This paper proposes the implementation of the Mumford and Shah functional without using complex operations such as multiplications and divisions. Our goal is to show that the achieved results in terms of performance/complexity trade-off are well suited for video applications of the Mumford and Shah functional, such as motion estimation based on segmentation techniques. To this purpose, two implementations, with and without multiplications, have been developed and ported on a DSP board that can get frames from a camera and play out the results on a standard VGA monitor: reported results show a relative speed-up of a factor of 3 for the multiplierless version with no visual quality degradation. [ABSTRACT FROM AUTHOR]

Abstract: Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720×480 video sequences at 30 frames/s and grant more than 50Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip). [ABSTRACT FROM AUTHOR]

A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logic and 187.2 kbit of memory, whereas the complete decoder requires 167.7 kgate and 1163 kbit. [ABSTRACT FROM AUTHOR]

This paper describes the analysis of the Mumford and Shah functional from the implementation point of view. Our goal is to show results in terms of complexity for real-time applications, such as motion estimation based on segmentation techniques, of the Mumford and Shah functional. Moreover, the sensitivity to finite precision representation is addressed, a fast VLSI architecture is described, and results obtained for its complete implementation on a 0.13 μm standard cells technology are presented. [ABSTRACT FROM AUTHOR]

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]

Machine learning (ML) is widely used today, especially through deep neural networks (DNNs); however, increasing computational load and resource requirements have led to cloud-based solutions. To address this problem, a new generation of networks has emerged called spiking neural networks (SNNs), which mimic the behavior of the human brain to improve efficiency and reduce energy consumption. These networks often process large amounts of sensitive information, such as confidential data, and thus privacy issues arise. Homomorphic encryption (HE) offers a solution, allowing calculations to be performed on encrypted data without decrypting them. This research compares traditional DNNs and SNNs using the Brakerski/Fan-Vercauteren (BFV) encryption scheme. The LeNet-5 and AlexNet models, widely-used convolutional architectures, are used for both DNN and SNN models based on their respective architectures, and the networks are trained and compared using the FashionMNIST dataset. The results show that SNNs using HE achieve up to 40% higher accuracy than DNNs for low values of the plaintext modulus t, although their execution time is longer due to their time-coding nature with multiple time steps. [ABSTRACT FROM AUTHOR]

Heterogeneous systems on a single chip composed of a central processing unit, graphics processing unit (GPU), and field-programmable gate array (FPGA) are expected to emerge in the near future. In this context, the system on chip can be dynamically adapted to employ different architectures for execution of data-intensive applications. Motion estimation (ME) is one such task that can be accelerated using FPGA and GPU for high-performance H.264/Advanced Video Coding encoder implementation. This paper presents an inherent parallel low-complexity rate-distortion (RD) optimized fast ME algorithm well suited for parallel implementations, eliminating various data dependencies caused by a reliance on spatial predictions. In addition, this paper provides details of the GPU and FPGA implementations of the parallel algorithm by using OpenCL and Very High Speed Integrated Circuits (VHSIC) Hardware Descriptive Language (VHDL), respectively, and presents a practical performance comparison between the two implementations. The experimental results show that the proposed scheme achieves significant speedup on GPU and FPGA, and has comparable RD performance with respect to sequential fast ME algorithm. [ABSTRACT FROM AUTHOR]

Features of the JPEG2000 compression standard include coding efficiency at low bit rates. However, its compressed bit stream is sensitive to transmission error. This paper presents three techniques to reduce both the computational complexity and the memory requirement in the ternary MQ arithmetic decoding. Such coders introduce a controlled degree of redundancy during the encoding process, which can be exploited at the decoder side in order to detect and correct errors. Our proposed techniques result in a substantial saving of decoding time and memory usage, with no or little degradation in the PSNR metric. [ABSTRACT FROM AUTHOR]

Deals with the design and implementation of an image transform coding algorithm based on the integer wavelet transform (IWT). Difficulty of compressing still images; Discussion of the lifting scheme and the factorization of the polyphase matrix; Effect of finite computer precision; Architecture for the IWT implementation by means of the lossy performance.

Hardware implementations can provide significant speedup and saving for video compression applications. In this work we focus on the transform coding sub-module analyzing the performance required by actual encoder implementations. We show that the throughput assumption about the transform sub-module in most research works is overly optimistic since it does not consider the complexity of a rate-distortion optimized video coding process. Many HEVC coding options are compared in terms of impact on quality and throughput, so to recommend the most efficient settings without excessively penalizing quality. Moreover, comparisons with the AVC standard show that, in general, HEVC presents much higher complexity to deliver its claimed compression advantages. Finally, a practical case study is shown to highlight how the proposed transform throughput analysis could be used to determine the throughput for a transform sub-module hardware design. [ABSTRACT FROM AUTHOR]

Capsule Networks (CapsNets) preserve the hierarchical spatial relationships between objects, and thereby bear the potential to surpass the performance of traditional Convolutional Neural Networks (CNNs) in performing tasks like image classification. This makes CapsNets suitable for the smart cyber–physical systems (CPS), where a large amount of training data may not be available. A large body of work has explored adversarial examples for CNNs, but their effectiveness on CapsNets has not yet been studied systematically. In our work, we perform an analysis to study the vulnerabilities in CapsNets to adversarial attacks. These perturbations, added to the test inputs, are small and imperceptible to humans, but can fool the network to mispredict. We propose a greedy algorithm to automatically generate imperceptible adversarial examples in a black-box attack scenario. We show that this kind of attacks, when applied to the German Traffic Sign Recognition Benchmark and CIFAR10 datasets, mislead CapsNets in making a correct classification, which can be catastrophic for smart CPS, like autonomous vehicles. Moreover, we apply the same kind of adversarial attacks to a 5-layer CNN (LeNet), to a 9-layer CNN (VGGNet), and to a 20-layer CNN (ResNet), and analyze the outcome, compared to the CapsNets, to study their different behaviors under the adversarial attacks. [ABSTRACT FROM AUTHOR]

Falls in the home environment are a primary cause of injury in older adults. According to the U.S. Centers for Disease Control and Prevention, every year, one in four adults 65 years of age and older reports experiencing a fall. A variety of different technologies have been proposed to detect fall events. However, the need to detect all fall instances (i.e., to avoid false negatives) has led to the development of systems marked by high sensitivity and hence a significant number of false alarms. The occurrence of false alarms causes frequent and unnecessary calls to emergency response centers, which are critical resources that should be utilized only when necessary. Besides, false alarms decrease the level of confidence of end-users in the fall detection system with a negative impact on their compliance with using the system (e.g., wearing the sensor enabling the detection of fall events). Herein, we present a novel approach aimed to augment traditional fall detection systems that rely on wearable sensors and fall detection algorithms. The proposed approach utilizes a UWB-based tracking system and a home robot. When the fall detection system generates an alarm, the alarm is relayed to a base station that utilizes a UWB-based tracking system to identify where the older adult and the robot are so as to enable navigating the environment using the robot and reaching the older adult to check if he/she experienced a fall. This approach prevents unnecessary calls to emergency response centers while enabling a tele-presence using the robot when appropriate. In this paper, we report the results of a novel fall detection algorithm, the characteristics of the alarm notification system, and the accuracy of the UWB-based tracking system that we implemented. The fall detection algorithm displayed a sensitivity of 99.0% and a specificity of 97.8%. The alarm notification system relayed all simulated alarm notification instances with a maximum delay of 106 ms. The UWB-based tracking system was found to be suitable to locate radio tags both in line-of-sight and in no-line-of-sight conditions. This result was obtained by using a machine learning-based algorithm that we developed to detect and compensate for the multipath effect in no-line-of-sight conditions. When using this algorithm, the error affecting the estimated position of the radio tags was smaller than 0.2 m, which is satisfactory for the application at hand. [ABSTRACT FROM AUTHOR]

In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC. [ABSTRACT FROM AUTHOR]