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This paper gives an explanation that SET pulse-width modulation in bulk CMOS devices happens due to negative bias temperature instability (NBTI). To investigate this, we propose and implement a stress adjustable pulse-width measurement circuit. Measurement results of test chips fabricated in a 65nm bulk CMOS process clearly show that pulse-width broadening and shrinking depend on the condition of static and dynamic stress before the pulse propagation. The measured dependency of pulse-width modulation on supply voltage is well correlated with that of NBTI model. We also point out that soft error rate computed from SET pulse-width distribution measured under static stress is pessimistic. [ABSTRACT FROM AUTHOR]

This paper gives an explanation that SET pulse-width modulation in bulk CMOS devices happens due to negative bias temperature instability (NBTI). To investigate this, we propose and implement a stress adjustable pulse-width measurement circuit. Measurement results of test chips fabricated in a 65nm bulk CMOS process clearly show that pulse-width broadening and shrinking depend on the condition of static and dynamic stress before the pulse propagation. The measured dependency of pulse-width modulation on supply voltage is well correlated with that of NBTI model. We also point out that soft error rate computed from SET pulse-width distribution measured under static stress is pessimistic. [ABSTRACT FROM PUBLISHER]

In this paper, the soft error rate (SER) induced by neutrons in 65-nm 10T static random access memory (SRAM) is measured over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is around eight times that at 1.0 V. The dependence of multiple cell upsets (MCUs) on the supply voltage and on the distance between well ties is also investigated. The dependence of the MCU rate on the supply voltage between 1.0 and 0.5 V is small and increases as the voltage is reduced below 0.5 V. This is because the effect of another mechanism, such as charge-sharing, becomes larger in the subthreshold region, rather than the parasitic bipolar effect, which is considered the dominant mechanism causing MCUs in SRAM at the nominal supply voltage in our design. [ABSTRACT FROM AUTHOR]

Configuration random access memory (CRAM), which consists of the static random access memory susceptible to single event upset (SEU), configures all of the user logic in field-programmable gate array (FPGA). In this article, we evaluate the impact of SEU in CRAM on the image-based lane tracking for autonomous driving via neutron irradiation experiments. In the experiments, the cross section of bit upsets and its corresponding single event function interrupt (SEFI) in the logic function of image processing are measured. By using a virtual driving environment, we observe whether a bit upset finally induces a severe SEFI of the system failure. The system failure is observed by an abnormal behavior on the virtual autonomous car driving by lane tracking. Experimental results show the bit upset has a maximum probability of 23% to induce SEFI and finally 8% of the bit upsets lead to failures in lane tracking. All the SEFIs observed in irradiation experiments are reproduced in fault injections with the same bit address. The cross section of SEFI was estimated in fault injections with reasonable precision. Moreover, we evaluate the improvement of system reliability by the error correction against soft errors. Our evaluation result shows that the error correction within the period of two-frame processing time could reduce the 74% SEFI cross section, but it has little benefit for system failure cross section if an error happens during the period of the image processing. [ABSTRACT FROM AUTHOR]

Characterizing low-energy neutrons (<10 MeV)-induced single-event upsets (SEUs) and multiple cells upsets (MCUs) is essential to validate the current standard for terrestrial soft error rate (SER) and investigate its enhancement. Following our preliminary analysis on the contribution of the low-energy neutrons to the total terrestrial SER at the nominal operating voltage of 1.0 V by Liao et al. (2020), this article newly presents and analyzes the data measured at the low operating voltage of 0.4 V. The dependence of SEU cross section on the neutron energy is similar between the operating voltages of 0.4 and 1.0 V, including onset energy of around 6 MeV. The existence of MCUs at 4.1-MeV neutrons was also confirmed at both the operating voltages. Based on the measurement, we approximate the dependence of SEU and MCU cross sections as Weibull functions of the neutron energy. The terrestrial SER of SEUs and MCUs was calculated by folding the Weibull function and the flux spectrum. The calculated result indicates that the SER originating from the low-energy neutrons is less than 6% in the terrestrial environment at New York and Tokyo City. We confirm that disregarding the flux of neutrons below 10 MeV in the acceleration factor calculation at accelerated neutron tests, which follows the current standard defined in JESD89, could give a reasonable SER estimation accuracy for both SEUs and MCUs. On the other hand, for covering the beams having an extremely high proportion of low-energy neutrons, considering the flux of neutrons above 6 MeV would be an option for better SER estimation. [ABSTRACT FROM AUTHOR]