Search

Many recent multilevel inverter papers end up with voltage total harmonic distortion (THD) values obtained from numerical voltage spectrum calculations (measurements). Motivated by IEEE Standard 519, a part of the multilevel research community uses a limited harmonic count to evaluate the multilevel voltage quality. First, this causes significant voltage THD underestimation, particularly for relatively high frequency PWM. Second, for a three-phase star-connected balanced load with an isolated neutral and phase symmetric modulation strategy, the calculated load line and phase voltage THD become different. However, simple considerations show that line and phase voltage THDs are essentially the same in this case. It may be difficult to judge about the multilevel voltage quality given a numerically calculated (measured) voltage THD value that may be subject to computation errors. Presented are simple smooth hyperbolic voltage THD upper and lower bound approximations for single- and three-phase inverters with nearest synchronous switching. They are valid for arbitrary modulation indices and uniformly distributed level counts and may practically serve as good reference values. [ABSTRACT FROM PUBLISHER]

ABSTRACT Flying capacitor converters (FCCs) are recently attracting considerable interest because of their inherent natural voltage balancing property. We develop a sampled-data model for a single-phase single-leg three-level FCC. This provides a closed-form expression for the system dynamic behavior after each switching cycle. Analysis of this model provides considerable insight on the FCC and its natural balancing property. In particular, we prove that the natural balancing property indeed holds whenever the switching frequency is sufficiently high. We also rigorously analyze dynamic properties such as the capacitor time constant and relate them to the parameter values of the load, carrier frequency and duty ratio. These results shed light on the intricate relationship between the FCC parameters and its short- and long-term dynamic behavior. Copyright © 2011 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Voltage total harmonic distortion and quadratic voltage ripple criteria are accepted figures of merit of a multilevel pulse width modulation (PWM) converter voltage quality. The dominating frequency domain approach does not deliver simple closed-form expressions and practically requires accounting up to 40–50 switching harmonics. Assuming infinitely high switching frequency, suggested time domain approach to a multilevel multiphase PWM voltage quality evaluation provides closed-form piece-wise analytical solutions. These simple formulas clearly reveal the dependence on modulation index for arbitrary voltage level and odd phase numbers. The results are applicable to any type of multilevel converters (including interleaved, open winding and other) operated with nearest level/nearest space vector modulation and relatively high switching frequency. [ABSTRACT FROM PUBLISHER]

Presents a comments on the paper, "Nearest and non-nearest three vector modulations of NPCI using two-level space vector diagram - a novel approach," (Babu, N. and Agarwal, P.), IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, 2013. [ABSTRACT FROM AUTHOR]

A letter to the editor is presented in response to the article "A variable switching frequency PWM technique for induction motor drive to spread acoustic noise spectrum with reduced current ripple," by A.C. Binojkumar et al., published in a previous issue of the journal.

Presents a discussion on the following paper, ?Electrical machine PWM loss evaluation basics (Ruderman, A. and Welch,R.) in Proc. Int. Conf. Energy Efficiency Motor Driven Syst.,Sep. 2005, vol. 1, pp. 58?68. [ABSTRACT FROM AUTHOR]

A new implementation of an iron-loss model for laminated magnetic cores in the MATLAB/Simulink environment is proposed in this paper. The model is based on numerically solving a one-dimensional diffusion problem for the eddy currents in the core lamination and applying an accurate hysteresis model as the constitutive law. An excess loss model is also considered. The model is identified merely based on the catalog data provided by the core material manufacturer. The implementation is validated with analytical and finite-element models and experimentally in the case of a toroidal inductor supplied from a GaN FET full-bridge inverter with 5–500 kHz switching frequencies and a deadtime of 300 ns. Despite the simple identification, a good correspondence is observed between the simulated and measured iron losses, the average difference being 3.3% over the wide switching frequency range. It is shown that accounting for the skin effect in the laminations is significant, in order to correctly model the iron losses at different switching frequencies. Some differences between the measured and simulated results at high switching frequencies are also discussed. The model is concluded to be applicable for designing and analyzing laminated magnetic cores in combination with power-electronics circuits. The Simulink models are openly available. [ABSTRACT FROM AUTHOR]

Power electronic converters for medium- and high-power/voltage applications employ low-frequency fundamental switching frequencies and, therefore, minimize switching losses. There are two main control techniques of switching angle estimation; total harmonic distortion (THD) minimization and selective harmonic elimination (SHE). In case of the first control technique, the switching angles are found based on THD minimization without being specifically focused on eliminating some exact harmonics. For the SHE control technique, all degrees of freedom, due to available number of switching angles, is used for the elimination of certain low-order harmonics. The basic idea of combining those two control techniques consists of using some degrees of freedom for eliminating certain harmonics and using the others for minimizing the remaining THD content. This generalized problem formulation includes classic minimal THD and SHE problems as special cases. Theoretical developments are verified by the set of experimental cases for the voltage and current THDs selecting characteristic working points over the modulation index range. [ABSTRACT FROM AUTHOR]

This paper presents the optimization technique for minimizing the voltage and current total harmonic distortion (THD) in a single-phase multilevel inverter controlled by staircase modulation. The previously reported research generally considered the optimal THD problem in the frequency domain, taking into account a limited harmonic number. The novelty of the suggested approach is that voltage and current minimal THD problems are being formulated in the time domain as constrained optimization ones, making it possible to determine the optimal switching angles. In this way, all switching harmonics can be considered. The target function expression becomes very compact and existing efficient solvers for this kind of optimization problems can find a solution in negligible processor time. Current THD is understood as voltage frequency weighted THD that assumes pure inductive load--this approximation is practically accurate for inductively dominant RL-loads. In this study, the optimal switching angles and respective minimal THD values were obtained for different inverter level counts and overall fundamental voltage magnitude (modulation index) dynamic range. Developments are easily modified to cover multilevel inverter grid-connected applications. The results have been verified by experimental tests. [ABSTRACT FROM AUTHOR]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

The measurement method on the basis of locked rotor tests has been developed for the estimation of magnet PWM carrier eddy current loss in synchronous machines. In the measurement, the magnet eddy current loss is separated from the other losses by subtracting the loss of the machine without the magnets from that with the magnets under the appropriate control of armature currents and voltages. The 3-D finite element analysis is also carried out in order to confirm the validity of the proposed measurement method. The measured and calculated results are found to be in good agreement. It is clarified that the magnet eddy current loss of the machine can be predicted from the results of the proposed measurement method. [ABSTRACT FROM AUTHOR]

This paper presents a novel optimization technique for Switched Capacitor Converters (SCCs). The optimization focuses on minimizing the SCC equivalent resistance by adjusting MOSFET widths and switching duty cycles. The optimized SCC parameters are obtained from numerical optimization with constant total transistor width and switching period constraints. The transistor carrier mobilities and gate-to-source voltages are accounted during the optimization. A Fibonacci SCC with two flying capacitors is used as an example and is simulated in a 65 ​nm low-power process. By comparing SCC parameters before and after the optimization, we obtain certain performance improvements. Particularly, at a switching frequency of 10 MHz and 50 Ω load, the optimized design shows improvement in average and minimum output voltage parameters by 2.5% and 4.1%, respectively, which are caused by 20.6% reduction of the equivalent resistance. The output voltage ripple is also decreased by 22.4%. By sweeping the duty cycle and transistor widths in simulation, the optimized parameters show nearly the best performance. [ABSTRACT FROM AUTHOR]

This work applies unequal duty cycle to switched-capacitor (SC) dc-dc converters to improve its output ripple as well as the power conversion efficiency. By adjusting the duty cycle, the capacitor charge and discharge states are reasonably balanced. Therefore, we effectively reduce the output ripple and the charge redistribution loss, improving the efficiency. A SC converter verifies this scheme with voltage conversion ratios (VCRs) of 1/4 and 1/3, in a 65 ​nm CMOS low-power process. Operating with a switching frequency of 33 ​MHz, an input voltage of 2.4 ​V, an output range of 0.5–25 ​mA, and a VCR of 1/4, the peak efficiency increases by 1.0% and the output ripple drops by 43.6%, when compared with the equal duty cycle mode. With the input voltage equal to 1.8 ​V and the VCR ​= ​1/3, the peak efficiency increases by 0.7% and the output ripple reduces by 48.0%, compared to the equal duty cycle mode. [ABSTRACT FROM AUTHOR]

Cascade H-bridge (CHB) inverter is an attractive choice for integration of DC sources of different nature, e.g., for distributed generation with energy storage, photovoltaic generation, etc. In general, non-equal DC voltage sources can affect the total harmonic distortion (THD) of the CHB by introducing undesirable low-frequency subharmonics. This paper investigates different level-shifted (LS) and phase-shifted (PS) pulse width modulation (PWM) strategies for single- and three-phase cascade H-bridge inverters with non-equal DC sources from the load current THD minimization perspective. The best current quality is provided by LS PWM, as reported in the literature. The paper provides a simple time domain explanation of LS PWM superiority. However, PS PWM may be a preferable choice for practical applications due to fair power and loss sharing across individual H-bridges. The paper explains how to obtain the best current quality by PS PWM carriers' order arrangement (DC sources switching sequence selection). [ABSTRACT FROM AUTHOR]